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Support targets that do not use i8 shift amounts.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19707 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-01-19 22:31:21 +00:00
parent 6fb5a4a5f8
commit 2c49f27955
1 changed files with 4 additions and 0 deletions
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4
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -450,6 +450,10 @@ void SelectionDAGLowering::visitBr(BranchInst &I) {
void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode) { void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode) {
SDOperand Op1 = getValue(I.getOperand(0)); SDOperand Op1 = getValue(I.getOperand(0));
SDOperand Op2 = getValue(I.getOperand(1)); SDOperand Op2 = getValue(I.getOperand(1));
if (isa<ShiftInst>(I))
Op2 = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), Op2);
setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
} }