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Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146219 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2011-12-09 01:16:26 +00:00
parent bd3825ecd1
commit 2dd0353fec
2 changed files with 19 additions and 4 deletions
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7
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -1483,9 +1483,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
SDValue InnerOp = InOp.getNode()->getOperand(0);
EVT InnerVT = InnerOp.getValueType();
if ((APInt::getHighBitsSet(BitWidth,
BitWidth - InnerVT.getSizeInBits()) &
DemandedMask) == 0 &&
unsigned InnerBits = InnerVT.getSizeInBits();
if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
isTypeDesirableForOp(ISD::SHL, InnerVT)) {
EVT ShTy = getShiftAmountTy(InnerVT);
if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
@ -1555,7 +1554,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// always convert this into a logical shr, even if the shift amount is
// variable. The low bit of the shift cannot be an input sign bit unless
// the shift amount is >= the size of the datatype, which is undefined.
if (DemandedMask == 1)
if (NewMask == 1)
return TLO.CombineTo(Op,
TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
Op.getOperand(0), Op.getOperand(1)));

16
test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll Normal file
View File

@ -0,0 +1,16 @@
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g4 | FileCheck %s
define void @test(i32* nocapture %x, i64* %xx, i32* %yp) nounwind uwtable ssp {
entry:
%yy = load i32* %yp
%y = add i32 %yy, 1
%z = zext i32 %y to i64
%z2 = shl i64 %z, 32
store i64 %z2, i64* %xx, align 4
ret void
; CHECK: test:
; CHECK: sldi {{.*}}, {{.*}}, 32
; Note: it's okay if someday CodeGen gets smart enough to optimize out
; the shift.
}