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fix typos in comments; NFC

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308126 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hiroshi Inoue 2017-07-16 07:48:48 +00:00
parent a72a0bef4d
commit 2dd9bf3147
4 changed files with 5 additions and 5 deletions
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2
lib/Target/AArch64/AArch64InstrInfo.h
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@ -366,7 +366,7 @@ enum AArch64FrameOffsetStatus {
/// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
/// use an offset.eq /// use an offset.eq
/// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
/// rewriten in @p MI. /// rewritten in @p MI.
/// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
/// amount that is off the limit of the legal offset. /// amount that is off the limit of the legal offset.
/// If set, @p OutUseUnscaledOp will contain the whether @p MI should be /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be

2
lib/Target/AArch64/AArch64RegisterInfo.cpp
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@ -74,7 +74,7 @@ const uint32_t *
AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF, AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
CallingConv::ID CC) const { CallingConv::ID CC) const {
if (CC == CallingConv::GHC) if (CC == CallingConv::GHC)
// This is academic becase all GHC calls are (supposed to be) tail calls // This is academic because all GHC calls are (supposed to be) tail calls
return CSR_AArch64_NoRegs_RegMask; return CSR_AArch64_NoRegs_RegMask;
if (CC == CallingConv::AnyReg) if (CC == CallingConv::AnyReg)
return CSR_AArch64_AllRegs_RegMask; return CSR_AArch64_AllRegs_RegMask;

4
lib/Target/ARM/ARMBaseRegisterInfo.cpp
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@ -117,7 +117,7 @@ ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
CallingConv::ID CC) const { CallingConv::ID CC) const {
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
if (CC == CallingConv::GHC) if (CC == CallingConv::GHC)
// This is academic becase all GHC calls are (supposed to be) tail calls // This is academic because all GHC calls are (supposed to be) tail calls
return CSR_NoRegs_RegMask; return CSR_NoRegs_RegMask;
if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() && if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
@ -163,7 +163,7 @@ ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
// both or otherwise does not want to enable this optimization, the function // both or otherwise does not want to enable this optimization, the function
// should return NULL // should return NULL
if (CC == CallingConv::GHC) if (CC == CallingConv::GHC)
// This is academic becase all GHC calls are (supposed to be) tail calls // This is academic because all GHC calls are (supposed to be) tail calls
return nullptr; return nullptr;
return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
: CSR_AAPCS_ThisReturn_RegMask; : CSR_AAPCS_ThisReturn_RegMask;

2
test/MC/ARM/virtexts-thumb.s
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@ -50,7 +50,7 @@
# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] # CHECK-THUMB: [0xde,0xf3,0x00,0x8f]
# SUBS PC, LR, #0 should have the same encoding as ERET. # SUBS PC, LR, #0 should have the same encoding as ERET.
# The conditional forms can't be tested becuse the ARM assembler parser doesn't # The conditional forms can't be tested because the ARM assembler parser doesn't
# accept SUBS<cond> PC, LR, #<imm>, only the unconditonal form is allowed. This # accept SUBS<cond> PC, LR, #<imm>, only the unconditonal form is allowed. This
# is due to the way that the custom parser handles optional operands; see the # is due to the way that the custom parser handles optional operands; see the
# FIXME in ARM/AsmParser/ARMAsmParser.cpp. # FIXME in ARM/AsmParser/ARMAsmParser.cpp.