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fix typos in comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308126 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -366,7 +366,7 @@ enum AArch64FrameOffsetStatus {
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/// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
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/// use an offset.eq
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/// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
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/// rewriten in @p MI.
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/// rewritten in @p MI.
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/// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
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/// amount that is off the limit of the legal offset.
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/// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
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@ -74,7 +74,7 @@ const uint32_t *
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AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const {
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if (CC == CallingConv::GHC)
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// This is academic becase all GHC calls are (supposed to be) tail calls
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// This is academic because all GHC calls are (supposed to be) tail calls
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return CSR_AArch64_NoRegs_RegMask;
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if (CC == CallingConv::AnyReg)
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return CSR_AArch64_AllRegs_RegMask;
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@ -117,7 +117,7 @@ ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const {
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const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
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if (CC == CallingConv::GHC)
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// This is academic becase all GHC calls are (supposed to be) tail calls
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// This is academic because all GHC calls are (supposed to be) tail calls
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return CSR_NoRegs_RegMask;
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if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
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@ -163,7 +163,7 @@ ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
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// both or otherwise does not want to enable this optimization, the function
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// should return NULL
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if (CC == CallingConv::GHC)
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// This is academic becase all GHC calls are (supposed to be) tail calls
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// This is academic because all GHC calls are (supposed to be) tail calls
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return nullptr;
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return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
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: CSR_AAPCS_ThisReturn_RegMask;
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@ -50,7 +50,7 @@
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# CHECK-THUMB: [0xde,0xf3,0x00,0x8f]
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# SUBS PC, LR, #0 should have the same encoding as ERET.
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# The conditional forms can't be tested becuse the ARM assembler parser doesn't
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# The conditional forms can't be tested because the ARM assembler parser doesn't
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# accept SUBS<cond> PC, LR, #<imm>, only the unconditonal form is allowed. This
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# is due to the way that the custom parser handles optional operands; see the
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# FIXME in ARM/AsmParser/ARMAsmParser.cpp.
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