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[ImplicitNullCheck] Extend canReorder scope
Summary: This change allows a re-order of two intructions if their uses are overlapped. Patch by Serguei Katkov! Reviewers: reames, sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29120 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293775 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjoy Das
parent
ab1df8f850
commit
2e079eaf6b
@ -253,7 +253,7 @@ bool ImplicitNullChecks::canReorder(const MachineInstr *A,
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unsigned RegB = MOB.getReg();
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if (TRI->regsOverlap(RegA, RegB))
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if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef()))
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return false;
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}
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}
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@ -310,7 +310,7 @@ ImplicitNullChecks::isSuitableMemoryOp(MachineInstr &MI, unsigned PointerReg,
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// lookup due to this condition will fail for any further instruction.
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for (auto *PrevMI : PrevInsts)
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for (auto &PrevMO : PrevMI->operands())
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if (PrevMO.isReg() && PrevMO.getReg() &&
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if (PrevMO.isReg() && PrevMO.getReg() && PrevMO.isDef() &&
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TRI->regsOverlap(PrevMO.getReg(), PointerReg))
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return SR_Impossible;
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@ -367,7 +367,8 @@ bool ImplicitNullChecks::canHoistLoadInst(
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// The Dependency can't be re-defining the base register -- then we won't
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// get the memory operation on the address we want. This is already
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// checked in \c IsSuitableMemoryOp.
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assert(!TRI->regsOverlap(DependenceMO.getReg(), PointerReg) &&
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assert(!(DependenceMO.isDef() &&
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TRI->regsOverlap(DependenceMO.getReg(), PointerReg)) &&
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"Should have been checked before!");
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}
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@ -135,6 +135,33 @@ define i32 @imp_null_check_via_mem_comparision(i32* %x, i32 %val) {
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ret i32 200
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}
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define i32 @imp_null_check_gep_load_with_use_dep(i32* %x, i32 %a) {
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; CHECK-LABEL: imp_null_check_gep_load_with_use_dep:
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; CHECK: [[BB0_imp_null_check_gep_load_with_use_dep:L[^:]+]]:
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; CHECK: movl (%rdi), %eax
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; CHECK: addl %edi, %esi
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; CHECK: leal 4(%rax,%rsi), %eax
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; CHECK: retq
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; CHECK: [[BB1_imp_null_check_gep_load_with_use_dep:LBB5_[0-9]+]]:
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; CHECK: movl $42, %eax
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; CHECK: retq
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%x.loc = getelementptr i32, i32* %x, i32 1
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%y = ptrtoint i32* %x.loc to i32
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%b = add i32 %a, %y
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%t = load i32, i32* %x
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%z = add i32 %t, %b
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ret i32 %z
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}
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!0 = !{}
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; CHECK-LABEL: __LLVM_FaultMaps:
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@ -147,7 +174,7 @@ define i32 @imp_null_check_via_mem_comparision(i32* %x, i32 %val) {
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; CHECK-NEXT: .short 0
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; # functions:
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; CHECK-NEXT: .long 5
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; CHECK-NEXT: .long 6
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; FunctionAddr:
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; CHECK-NEXT: .quad _imp_null_check_add_result
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@ -175,6 +202,19 @@ define i32 @imp_null_check_via_mem_comparision(i32* %x, i32 %val) {
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; Fault[0].HandlerOffset:
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; CHECK-NEXT: .long [[BB1_imp_null_check_gep_load]]-_imp_null_check_gep_load
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; FunctionAddr:
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; CHECK-NEXT: .quad _imp_null_check_gep_load_with_use_dep
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; NumFaultingPCs
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; CHECK-NEXT: .long 1
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; Reserved:
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; CHECK-NEXT: .long 0
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; Fault[0].Type:
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; CHECK-NEXT: .long 1
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; Fault[0].FaultOffset:
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; CHECK-NEXT: .long [[BB0_imp_null_check_gep_load_with_use_dep]]-_imp_null_check_gep_load_with_use_dep
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; Fault[0].HandlerOffset:
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; CHECK-NEXT: .long [[BB1_imp_null_check_gep_load_with_use_dep]]-_imp_null_check_gep_load_with_use_dep
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; FunctionAddr:
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; CHECK-NEXT: .quad _imp_null_check_hoist_over_unrelated_load
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; NumFaultingPCs
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@ -216,12 +256,14 @@ define i32 @imp_null_check_via_mem_comparision(i32* %x, i32 %val) {
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; OBJDUMP: FaultMap table:
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; OBJDUMP-NEXT: Version: 0x1
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; OBJDUMP-NEXT: NumFunctions: 5
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; OBJDUMP-NEXT: NumFunctions: 6
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; OBJDUMP-NEXT: FunctionAddress: 0x000000, NumFaultingPCs: 1
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; OBJDUMP-NEXT: Fault kind: FaultingLoad, faulting PC offset: 0, handling PC offset: 5
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; OBJDUMP-NEXT: FunctionAddress: 0x000000, NumFaultingPCs: 1
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; OBJDUMP-NEXT: Fault kind: FaultingLoad, faulting PC offset: 0, handling PC offset: 7
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; OBJDUMP-NEXT: FunctionAddress: 0x000000, NumFaultingPCs: 1
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; OBJDUMP-NEXT: Fault kind: FaultingLoad, faulting PC offset: 0, handling PC offset: 9
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; OBJDUMP-NEXT: FunctionAddress: 0x000000, NumFaultingPCs: 1
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; OBJDUMP-NEXT: Fault kind: FaultingLoad, faulting PC offset: 0, handling PC offset: 7
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; OBJDUMP-NEXT: FunctionAddress: 0x000000, NumFaultingPCs: 1
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; OBJDUMP-NEXT: Fault kind: FaultingLoad, faulting PC offset: 0, handling PC offset: 3
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@ -145,6 +145,35 @@
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attributes #0 = { "target-features"="+bmi,+bmi2" }
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define i32 @imp_null_check_gep_load_with_use_dep(i32* %x, i32 %a) {
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null: ; preds = %entry
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ret i32 42
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not_null: ; preds = %entry
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%x.loc = getelementptr i32, i32* %x, i32 1
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%y = ptrtoint i32* %x.loc to i32
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%b = add i32 %a, %y
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%t = load i32, i32* %x
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%z = add i32 %t, %b
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ret i32 %z
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}
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define i32 @imp_null_check_load_with_base_sep(i32* %x, i32 %a) {
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null: ; preds = %entry
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ret i32 42
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not_null: ; preds = %entry
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ret i32 undef
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}
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!0 = !{}
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...
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---
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@ -447,8 +476,8 @@ body: |
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name: use_alternate_load_op
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# CHECK-LABEL: use_alternate_load_op
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# CHECK: bb.0.entry:
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# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags
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# CHECK-NEXT: JE_1 %bb.2.is_null, implicit killed %eflags
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# CHECK: %r10 = FAULTING_LOAD_OP %bb.2.is_null, {{[0-9]+}}, killed %rdi, 1, _, 0, _
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# CHECK-NEXT: JMP_1 %bb.1.not_null
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# CHECK: bb.1.not_null
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alignment: 4
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@ -477,3 +506,66 @@ body: |
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RETQ %eax
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...
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---
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name: imp_null_check_gep_load_with_use_dep
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# CHECK: bb.0.entry:
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# CHECK: %eax = FAULTING_LOAD_OP %bb.2.is_null, {{[0-9]+}}, killed %rdi, 1, _, 0, _, implicit-def %rax :: (load 4 from %ir.x)
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# CHECK-NEXT: JMP_1 %bb.1.not_null
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '%rdi' }
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- { reg: '%rsi' }
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body: |
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bb.0.entry:
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successors: %bb.1.is_null(0x30000000), %bb.2.not_null(0x50000000)
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liveins: %rsi, %rdi
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TEST64rr %rdi, %rdi, implicit-def %eflags
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JE_1 %bb.1.is_null, implicit %eflags
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bb.2.not_null:
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liveins: %rdi, %rsi
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%rsi = ADD64rr %rsi, %rdi, implicit-def dead %eflags
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%eax = MOV32rm killed %rdi, 1, _, 0, _, implicit-def %rax :: (load 4 from %ir.x)
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%eax = LEA64_32r killed %rax, 1, killed %rsi, 4, _
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RETQ %eax
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bb.1.is_null:
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%eax = MOV32ri 42
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RETQ %eax
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...
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---
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name: imp_null_check_load_with_base_sep
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# CHECK: bb.0.entry:
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# CHECK: %rsi = ADD64rr %rsi, %rdi, implicit-def dead %eflags
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# CHECK-NEXT: %esi = FAULTING_LOAD_OP %bb.2.is_null, {{[0-9]+}}, killed %esi, %rdi, 1, _, 0, _, implicit-def dead %eflags
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# CHECK-NEXT: JMP_1 %bb.1.not_null
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '%rdi' }
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- { reg: '%rsi' }
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body: |
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bb.0.entry:
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successors: %bb.1.is_null(0x30000000), %bb.2.not_null(0x50000000)
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liveins: %rsi, %rdi
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TEST64rr %rdi, %rdi, implicit-def %eflags
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JE_1 %bb.1.is_null, implicit %eflags
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bb.2.not_null:
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liveins: %rdi, %rsi
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%rsi = ADD64rr %rsi, %rdi, implicit-def dead %eflags
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%esi = AND32rm killed %esi, %rdi, 1, _, 0, _, implicit-def dead %eflags
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%eax = MOV32rr %esi
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RETQ %eax
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bb.1.is_null:
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%eax = MOV32ri 42
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RETQ %eax
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...
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