RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-01-23 20:57:21 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Added missing 'rs1' field to F3_rdrs1imm13, 'rd' to F3_rdrs1rs2.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6618 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2003-06-05 00:39:45 +00:00
parent aeab1e163f
commit 2e7e8fadf8
1 changed files with 2 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/SparcV9/SparcV9_F3.td
View File

@ -75,14 +75,13 @@ class F3_rdrs1 : F3_rd {
}
// F3_rdrs1simm13 - Common class of instructions that have rd, rs1, and simm13
class F3_rdrs1simm13 : F3_rd {
class F3_rdrs1simm13 : F3_rdrs1 {
bits<13> simm13;
set Inst{12-0} = simm13;
}
// F3_rdrs1rs2 - Common class of instructions that have rd, rs1, and rs2 fields
class F3_rdrs1rs2 : F3_rs1 {
class F3_rdrs1rs2 : F3_rdrs1 {
bits<5> rs2;
set Inst{4-0} = rs2;
}