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https://github.com/RPCSX/llvm.git
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Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121439 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
1c952b9cc9
commit
2ea8ee7c76
@ -116,11 +116,11 @@ def : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem,
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FeatureFastUAMem]>;
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// Westmere is a similar machine to nehalem with some additional features.
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// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
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def : Proc<"westmere", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem,
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FeatureFastUAMem, FeatureAES]>;
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// Sandy Bridge does not have FMA
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// FIXME: Wikipedia says it does... it should have AES as well.
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def : Proc<"sandybridge", [FeatureSSE42, FeatureAVX, Feature64Bit]>;
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def : Proc<"westmere", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem,
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FeatureFastUAMem, FeatureAES, FeatureCLMUL]>;
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// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
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// rather than a superset.
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def : Proc<"sandybridge", [FeatureAVX, FeatureAES, FeatureCLMUL, Feature64Bit]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
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@ -61,7 +61,7 @@ def RetCC_X86_32_C : CallingConv<[
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// weirdly; this is really the sse-regparm calling convention) in which
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// case they use XMM0, otherwise it is the same as the common X86 calling
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// conv.
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CCIfInReg<CCIfSubtarget<"hasSSE2()",
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CCIfInReg<CCIfSubtarget<"hasXMMInt()",
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CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
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CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
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CCDelegateTo<RetCC_X86Common>
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@ -73,8 +73,8 @@ def RetCC_X86_32_Fast : CallingConv<[
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// SSE2.
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// This can happen when a float, 2 x float, or 3 x float vector is split by
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// target lowering, and is returned in 1-3 sse regs.
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CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
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CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
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CCIfType<[f32], CCIfSubtarget<"hasXMMInt()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
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CCIfType<[f64], CCIfSubtarget<"hasXMMInt()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
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// For integers, ECX can be used as an extra return register
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CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
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@ -163,12 +163,12 @@ def CC_X86_64_C : CallingConv<[
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// registers on Darwin.
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CCIfType<[x86mmx],
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CCIfSubtarget<"isTargetDarwin()",
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CCIfSubtarget<"hasSSE2()",
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CCIfSubtarget<"hasXMMInt()",
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CCPromoteToType<v2i64>>>>,
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// The first 8 FP/Vector arguments are passed in XMM registers.
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CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfSubtarget<"hasSSE1()",
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CCIfSubtarget<"hasXMM()",
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CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
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// The first 8 256-bit vector arguments are passed in YMM registers.
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@ -245,7 +245,7 @@ def CC_X86_64_GHC : CallingConv<[
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// Pass in STG registers: F1, F2, F3, F4, D1, D2
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CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfSubtarget<"hasSSE1()",
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CCIfSubtarget<"hasXMM()",
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CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
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]>;
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@ -263,7 +263,7 @@ def CC_X86_32_Common : CallingConv<[
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// The first 3 float or double arguments, if marked 'inreg' and if the call
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// is not a vararg call and if SSE2 is available, are passed in SSE registers.
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CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
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CCIfSubtarget<"hasSSE2()",
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CCIfSubtarget<"hasXMMInt()",
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CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
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// The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
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@ -362,7 +362,7 @@ def CC_X86_32_FastCC : CallingConv<[
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// The first 3 float or double arguments, if the call is not a vararg
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// call and if SSE2 is available, are passed in SSE registers.
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CCIfNotVarArg<CCIfType<[f32,f64],
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CCIfSubtarget<"hasSSE2()",
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CCIfSubtarget<"hasXMMInt()",
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CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
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// Doubles get 8-byte slots that are 8-byte aligned.
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@ -81,8 +81,8 @@ static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
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X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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: TargetLowering(TM, createTLOF(TM)) {
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Subtarget = &TM.getSubtarget<X86Subtarget>();
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X86ScalarSSEf64 = Subtarget->hasSSE2();
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X86ScalarSSEf32 = Subtarget->hasSSE1();
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X86ScalarSSEf64 = Subtarget->hasXMMInt();
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X86ScalarSSEf32 = Subtarget->hasXMM();
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X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
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RegInfo = TM.getRegisterInfo();
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@ -356,7 +356,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
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}
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if (Subtarget->hasSSE1())
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if (Subtarget->hasXMM())
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setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
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// We may not have a libcall for MEMBARRIER so we should lower this.
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@ -664,7 +664,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
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setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
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if (!UseSoftFloat && Subtarget->hasSSE1()) {
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if (!UseSoftFloat && Subtarget->hasXMM()) {
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addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
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setOperationAction(ISD::FADD, MVT::v4f32, Legal);
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@ -681,7 +681,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
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}
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if (!UseSoftFloat && Subtarget->hasSSE2()) {
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if (!UseSoftFloat && Subtarget->hasXMMInt()) {
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addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
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// FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
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@ -1043,7 +1043,7 @@ unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
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}
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unsigned Align = 4;
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if (Subtarget->hasSSE1())
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if (Subtarget->hasXMM())
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getMaxByValAlign(Ty, Align);
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return Align;
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}
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@ -1084,7 +1084,7 @@ X86TargetLowering::getOptimalMemOpType(uint64_t Size,
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} else if (!MemcpyStrSrc && Size >= 8 &&
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!Subtarget->is64Bit() &&
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Subtarget->getStackAlignment() >= 8 &&
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Subtarget->hasSSE2()) {
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Subtarget->hasXMMInt()) {
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// Do not use f64 to lower memcpy if source is string constant. It's
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// better to use i32 to avoid the loads.
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return MVT::f64;
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@ -1272,14 +1272,14 @@ X86TargetLowering::LowerReturn(SDValue Chain,
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// or SSE or MMX vectors.
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if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
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VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
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(Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
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(Subtarget->is64Bit() && !Subtarget->hasXMM())) {
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report_fatal_error("SSE register return with SSE disabled");
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}
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// Likewise we can't return F64 values with SSE1 only. gcc does so, but
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// llvm-gcc has never done it right and no one has noticed, so this
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// should be OK for now.
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if (ValVT == MVT::f64 &&
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(Subtarget->is64Bit() && !Subtarget->hasSSE2()))
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(Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
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report_fatal_error("SSE2 register return with SSE2 disabled");
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// Returns in ST0/ST1 are handled specially: these are pushed as operands to
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@ -1391,7 +1391,7 @@ X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
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// If this is x86-64, and we disabled SSE, we can't return FP values
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if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
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((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
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((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
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report_fatal_error("SSE register return with SSE disabled");
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}
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@ -1700,11 +1700,11 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
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TotalNumIntRegs);
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bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
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assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
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assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
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"SSE register cannot be used when SSE is disabled!");
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assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
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"SSE register cannot be used when SSE is disabled!");
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if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
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if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
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// Kernel mode asks for SSE to be disabled, so don't push them
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// on the stack.
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TotalNumXMMRegs = 0;
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@ -2055,7 +2055,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
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};
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unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
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assert((Subtarget->hasSSE1() || !NumXMMRegs)
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assert((Subtarget->hasXMM() || !NumXMMRegs)
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&& "SSE registers cannot be used when SSE is disabled");
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Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
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@ -7635,7 +7635,7 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
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assert(!UseSoftFloat &&
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!(DAG.getMachineFunction()
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.getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
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Subtarget->hasSSE1());
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Subtarget->hasXMM());
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}
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// Insert VAARG_64 node into the DAG
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@ -11689,7 +11689,7 @@ TargetLowering::ConstraintWeight
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break;
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case 'x':
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case 'Y':
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if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1())
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if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
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weight = CW_Register;
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break;
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case 'I':
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@ -11759,9 +11759,9 @@ LowerXConstraint(EVT ConstraintVT) const {
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// FP X constraints get lowered to SSE1/2 registers if available, otherwise
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// 'f' like normal targets.
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if (ConstraintVT.isFloatingPoint()) {
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if (Subtarget->hasSSE2())
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if (Subtarget->hasXMMInt())
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return "Y";
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if (Subtarget->hasSSE1())
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if (Subtarget->hasXMM())
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return "x";
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}
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@ -11991,10 +11991,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
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if (!Subtarget->hasMMX()) break;
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return std::make_pair(0U, X86::VR64RegisterClass);
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case 'Y': // SSE_REGS if SSE2 allowed
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if (!Subtarget->hasSSE2()) break;
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if (!Subtarget->hasXMMInt()) break;
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// FALL THROUGH.
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case 'x': // SSE_REGS if SSE1 allowed
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if (!Subtarget->hasSSE1()) break;
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if (!Subtarget->hasXMM()) break;
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switch (VT.getSimpleVT().SimpleTy) {
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default: break;
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@ -400,26 +400,26 @@ def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
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def HasCMov : Predicate<"Subtarget->hasCMov()">;
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def NoCMov : Predicate<"!Subtarget->hasCMov()">;
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// FIXME: temporary hack to let codegen assert or generate poor code in case
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// no AVX version of the desired intructions is present, this is better for
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// incremental dev (without fallbacks it's easier to spot what's missing)
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def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">;
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def HasMMX : Predicate<"Subtarget->hasMMX()">;
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def Has3DNow : Predicate<"Subtarget->has3DNow()">;
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def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
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def HasSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
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def HasSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
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def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
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def HasSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
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def HasSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
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def HasSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
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def HasSSE4A : Predicate<"Subtarget->hasSSE4A() && !Subtarget->hasAVX()">;
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def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
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def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
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def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
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def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
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def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
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def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
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def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
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def HasAVX : Predicate<"Subtarget->hasAVX()">;
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def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">;
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def HasAES : Predicate<"Subtarget->hasAES()">;
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def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
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def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
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def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
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def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
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def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
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def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
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def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
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def In32BitMode : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate;
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def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate;
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def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
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@ -436,7 +436,6 @@ def OptForSize : Predicate<"OptForSize">;
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def OptForSpeed : Predicate<"!OptForSize">;
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def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
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def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
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def HasAES : Predicate<"Subtarget->hasAES()">;
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//===----------------------------------------------------------------------===//
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// X86 Instruction Format Definitions.
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@ -712,6 +712,8 @@ def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
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"vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
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}
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def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>;
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def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
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"cvtsd2ss\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround FR64:$src))]>;
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@ -739,6 +741,8 @@ def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
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"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
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}
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def : Pat<(f64 (fextend FR32:$src)), (VCVTSS2SDrr FR32:$src, FR32:$src)>;
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def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
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"cvtss2sd\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fextend FR32:$src))]>, XS,
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@ -3680,7 +3684,7 @@ let Predicates = [HasSSE2] in
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(CVTSS2SDrm addr:$src)>;
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// bit_convert
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let Predicates = [HasSSE2] in {
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let Predicates = [HasXMMInt] in {
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def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
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def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
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def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
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@ -3713,6 +3717,10 @@ let Predicates = [HasSSE2] in {
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def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
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}
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let Predicates = [HasAVX] in {
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def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
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}
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// Move scalar to XMM zero-extended
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// movd to XMM register zero-extends
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let AddedComplexity = 15 in {
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@ -256,13 +256,13 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
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if ((ECX >> 9) & 1) X86SSELevel = SSSE3;
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if ((ECX >> 19) & 1) X86SSELevel = SSE41;
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if ((ECX >> 20) & 1) X86SSELevel = SSE42;
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if ((ECX >> 28) & 1) { HasAVX = true; X86SSELevel = NoMMXSSE; }
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bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
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bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
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HasCLMUL = IsIntel && ((ECX >> 1) & 0x1);
|
||||
HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
|
||||
HasAVX = ((ECX >> 28) & 0x1);
|
||||
HasAES = IsIntel && ((ECX >> 25) & 0x1);
|
||||
|
||||
if (IsIntel || IsAMD) {
|
||||
@ -316,11 +316,13 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
|
||||
ParseSubtargetFeatures(FS, CPU);
|
||||
// All X86-64 CPUs also have SSE2, however user might request no SSE via
|
||||
// -mattr, so don't force SSELevel here.
|
||||
if (HasAVX)
|
||||
X86SSELevel = NoMMXSSE;
|
||||
} else {
|
||||
// Otherwise, use CPUID to auto-detect feature set.
|
||||
AutoDetectSubtargetFeatures();
|
||||
// Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
|
||||
if (Is64Bit && X86SSELevel < SSE2)
|
||||
if (Is64Bit && !HasAVX && X86SSELevel < SSE2)
|
||||
X86SSELevel = SSE2;
|
||||
}
|
||||
|
||||
|
||||
@ -155,6 +155,8 @@ public:
|
||||
bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
|
||||
bool hasPOPCNT() const { return HasPOPCNT; }
|
||||
bool hasAVX() const { return HasAVX; }
|
||||
bool hasXMM() const { return hasSSE1() || hasAVX(); }
|
||||
bool hasXMMInt() const { return hasSSE2() || hasAVX(); }
|
||||
bool hasAES() const { return HasAES; }
|
||||
bool hasCLMUL() const { return HasCLMUL; }
|
||||
bool hasFMA3() const { return HasFMA3; }
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
|
||||
define void @zero() nounwind ssp {
|
||||
entry:
|
||||
; CHECK: vpxor
|
||||
; CHECK: vxorps
|
||||
; CHECK: vmovaps
|
||||
store <4 x float> zeroinitializer, <4 x float>* @z, align 16
|
||||
ret void
|
||||
|
||||
Loading…
Reference in New Issue
Block a user