From 2ead458ae8423d6ecaec7cbd45e1e2c71ce9e618 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Sun, 14 Nov 2010 22:03:15 +0000
Subject: [PATCH] lower PPC::MFCRpseud when transforming to MC, avoiding
 calling the aborting printSpecial() method.  This gets us to 8 failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119084 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/PowerPC/PPCAsmPrinter.cpp | 13 +++++++++++--
 lib/Target/PowerPC/PPCInstrInfo.td   |  7 +++++++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 039bb4dffac..8cd87de66d4 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -554,13 +554,22 @@ void PPCAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo,
 ///
 void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   if (UseInstPrinter) {
+    MCInst TmpInst;
+    
     // Lower multi-instruction pseudo operations.
     switch (MI->getOpcode()) {
     default: break;
-    // TODO: implement me.
+        
+    case PPC::MFCRpseud:
+      // Transform: %R3 = MFCRpseud %CR7
+      // Into:      %R3 = MFCR      ;; cr7
+      OutStreamer.AddComment(getRegisterName(MI->getOperand(1).getReg()));
+      TmpInst.setOpcode(PPC::MFCR);
+      TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
+      OutStreamer.EmitInstruction(TmpInst);
+      return;
     }
 
-    MCInst TmpInst;
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
     OutStreamer.EmitInstruction(TmpInst);
     return;
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index eb100ec7528..a6156c0c339 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1120,9 +1120,16 @@ def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
 // As it turns out, in all cases where we currently use this,
 // we're only interested in one subregister of it.  Represent this in the
 // instruction to keep the register allocator from becoming confused.
+//
+// FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
                        "mfcr $rT ${:comment} $FXM", SprMFCR>,
             PPC970_MicroCode, PPC970_Unit_CRU;
+            
+def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
+                     "mfcr $rT", SprMFCR>,
+                     PPC970_MicroCode, PPC970_Unit_CRU;
+
 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
                        "mfcr $rT, $FXM", SprMFCR>,
             PPC970_DGroup_First, PPC970_Unit_CRU;