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Move some simple-sched-specific instance vars to the simple scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26690 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -284,7 +284,6 @@ namespace llvm {
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class ScheduleDAG {
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public:
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SchedHeuristics Heuristic; // Scheduling heuristic
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SelectionDAG &DAG; // DAG of the current basic block
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MachineBasicBlock *BB; // Current basic block
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const TargetMachine &TM; // Target processor
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@ -292,38 +291,18 @@ namespace llvm {
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const MRegisterInfo *MRI; // Target processor register info
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SSARegMap *RegMap; // Virtual/real register map
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MachineConstantPool *ConstPool; // Target constant pool
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std::map<SDNode *, NodeInfo *> Map; // Map nodes to info
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unsigned NodeCount; // Number of nodes in DAG
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bool HasGroups; // True if there are any groups
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NodeInfo *Info; // Info for nodes being scheduled
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NIVector Ordering; // Emit ordering of nodes
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NodeGroup *HeadNG, *TailNG; // Keep track of allocated NodeGroups
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ScheduleDAG(SchedHeuristics hstc, SelectionDAG &dag, MachineBasicBlock *bb,
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ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
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const TargetMachine &tm)
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: Heuristic(hstc), DAG(dag), BB(bb), TM(tm), NodeCount(0),
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HasGroups(false), Info(NULL), HeadNG(NULL), TailNG(NULL) {}
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: DAG(dag), BB(bb), TM(tm) {}
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virtual ~ScheduleDAG() {
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if (Info)
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delete[] Info;
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NodeGroup *NG = HeadNG;
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while (NG) {
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NodeGroup *NextSU = NG->Next;
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delete NG;
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NG = NextSU;
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}
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};
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/// Run - perform scheduling.
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///
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MachineBasicBlock *Run();
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/// getNI - Returns the node info for the specified node.
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///
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NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
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/// isPassiveNode - Return true if the node is a non-scheduled leaf.
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///
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static bool isPassiveNode(SDNode *Node) {
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@ -346,9 +346,6 @@ MachineBasicBlock *ScheduleDAG::Run() {
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RegMap = BB->getParent()->getSSARegMap();
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ConstPool = BB->getParent()->getConstantPool();
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// Number the nodes
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NodeCount = std::distance(DAG.allnodes_begin(), DAG.allnodes_end());
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Schedule();
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return BB;
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}
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@ -189,7 +189,7 @@ public:
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const TargetMachine &tm, bool isbottomup,
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SchedulingPriorityQueue *priorityqueue,
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HazardRecognizer *HR)
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: ScheduleDAG(listSchedulingBURR, dag, bb, tm),
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: ScheduleDAG(dag, bb, tm),
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CurrCycle(0), isBottomUp(isbottomup),
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PriorityQueue(priorityqueue), HazardRec(HR) {
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}
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@ -188,24 +188,48 @@ public:
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///
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class ScheduleDAGSimple : public ScheduleDAG {
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private:
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SchedHeuristics Heuristic; // Scheduling heuristic
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ResourceTally<unsigned> Tally; // Resource usage tally
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unsigned NSlots; // Total latency
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static const unsigned NotFound = ~0U; // Search marker
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unsigned NodeCount; // Number of nodes in DAG
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std::map<SDNode *, NodeInfo *> Map; // Map nodes to info
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bool HasGroups; // True if there are any groups
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NodeInfo *Info; // Info for nodes being scheduled
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NIVector Ordering; // Emit ordering of nodes
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NodeGroup *HeadNG, *TailNG; // Keep track of allocated NodeGroups
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public:
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// Ctor.
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ScheduleDAGSimple(SchedHeuristics hstc, SelectionDAG &dag,
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MachineBasicBlock *bb, const TargetMachine &tm)
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: ScheduleDAG(hstc, dag, bb, tm), Tally(), NSlots(0) {
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: ScheduleDAG(dag, bb, tm), Heuristic(hstc), Tally(), NSlots(0),
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NodeCount(0), HasGroups(false), Info(NULL), HeadNG(NULL), TailNG(NULL) {
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assert(&TII && "Target doesn't provide instr info?");
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assert(&MRI && "Target doesn't provide register info?");
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}
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virtual ~ScheduleDAGSimple() {};
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virtual ~ScheduleDAGSimple() {
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if (Info)
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delete[] Info;
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NodeGroup *NG = HeadNG;
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while (NG) {
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NodeGroup *NextSU = NG->Next;
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delete NG;
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NG = NextSU;
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}
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}
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void Schedule();
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/// getNI - Returns the node info for the specified node.
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///
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NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
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private:
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static bool isDefiner(NodeInfo *A, NodeInfo *B);
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void IncludeNode(NodeInfo *NI);
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@ -826,6 +850,9 @@ void ScheduleDAGSimple::ScheduleForward() {
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/// Schedule - Order nodes according to selected style.
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///
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void ScheduleDAGSimple::Schedule() {
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// Number the nodes
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NodeCount = std::distance(DAG.allnodes_begin(), DAG.allnodes_end());
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// Set up minimum info for scheduling
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PrepareNodeInfo();
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// Construct node groups for flagged nodes
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