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[X86] Strengthen the setting of inline asm constraints.

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The setting of the inline asm constraints was implicitly relying on the
order of the register classes in the file generated by tablegen.
Since, we do not have any control on that order, make sure we do not
depend on it anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268953 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet 2016-05-09 19:01:35 +00:00
parent f9018a1eb7
commit 3024e4486b
1 changed files with 38 additions and 2 deletions
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40
lib/Target/X86/X86ISelLowering.cpp
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@ -30182,6 +30182,39 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
}
/// Check if \p RC is a general purpose register class.
/// I.e., GR* or one of their variant.
static bool isGRClass(const TargetRegisterClass &RC) {
switch (RC.getID()) {
case X86::GR8RegClassID:
case X86::GR8_ABCD_LRegClassID:
case X86::GR8_ABCD_HRegClassID:
case X86::GR8_NOREXRegClassID:
case X86::GR16RegClassID:
case X86::GR16_ABCDRegClassID:
case X86::GR16_NOREXRegClassID:
case X86::GR32RegClassID:
case X86::GR32_ABCDRegClassID:
case X86::GR32_TCRegClassID:
case X86::GR32_NOREXRegClassID:
case X86::GR32_NOAXRegClassID:
case X86::GR32_NOSPRegClassID:
case X86::GR32_NOREX_NOSPRegClassID:
case X86::GR32_ADRegClassID:
case X86::GR64RegClassID:
case X86::GR64_ABCDRegClassID:
case X86::GR64_TCRegClassID:
case X86::GR64_TCW64RegClassID:
case X86::GR64_NOREXRegClassID:
case X86::GR64_NOSPRegClassID:
case X86::GR64_NOREX_NOSPRegClassID:
case X86::LOW32_ADDR_ACCESSRegClassID:
return true;
default:
return false;
}
}
std::pair<unsigned, const TargetRegisterClass *>
X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint,
@ -30343,8 +30376,11 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
// return "eax". This should even work for things like getting 64bit integer
// registers when given an f64 type.
const TargetRegisterClass *Class = Res.second;
if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
// The generic code will match the first register class that contains the
// given register. Thus, based on the ordering of the tablegened file,
// the "plain" GR classes might not come first.
// Therefore, use a helper method.
if (isGRClass(*Class)) {
unsigned Size = VT.getSizeInBits();
if (Size == 1) Size = 8;
unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, Size);