diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp index a04d4b8cda1..6cb241a37a9 100644 --- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp +++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp @@ -1397,18 +1397,16 @@ void PhyRegAlloc::allocateStackSpace4SpilledLRs() { //---------------------------------------------------------------------------- -// The entry pont to Register Allocation +// The entry point to Register Allocation //---------------------------------------------------------------------------- void PhyRegAlloc::allocateRegisters() { - // make sure that we put all register classes into the RegClassList // before we call constructLiveRanges (now done in the constructor of // PhyRegAlloc class). // LRI.constructLiveRanges(); // create LR info - if (DEBUG_RA >= RA_DEBUG_LiveRanges) LRI.printLiveRanges(); @@ -1416,7 +1414,6 @@ void PhyRegAlloc::allocateRegisters() buildInterferenceGraphs(); // build IGs in all reg classes - if (DEBUG_RA >= RA_DEBUG_LiveRanges) { // print all LRs in all reg classes for ( unsigned rc=0; rc < NumOfRegClasses ; rc++) diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp index a04d4b8cda1..6cb241a37a9 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp @@ -1397,18 +1397,16 @@ void PhyRegAlloc::allocateStackSpace4SpilledLRs() { //---------------------------------------------------------------------------- -// The entry pont to Register Allocation +// The entry point to Register Allocation //---------------------------------------------------------------------------- void PhyRegAlloc::allocateRegisters() { - // make sure that we put all register classes into the RegClassList // before we call constructLiveRanges (now done in the constructor of // PhyRegAlloc class). // LRI.constructLiveRanges(); // create LR info - if (DEBUG_RA >= RA_DEBUG_LiveRanges) LRI.printLiveRanges(); @@ -1416,7 +1414,6 @@ void PhyRegAlloc::allocateRegisters() buildInterferenceGraphs(); // build IGs in all reg classes - if (DEBUG_RA >= RA_DEBUG_LiveRanges) { // print all LRs in all reg classes for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)