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Fix an assertion in the scheduler. PR11386. No testcase included because it's rather delicate.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146083 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2011-12-07 22:06:02 +00:00
parent 20aa12ae5c
commit 30c44e18bf
1 changed files with 2 additions and 3 deletions
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5
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@ -811,12 +811,11 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
I != E; ++I) {
if (I->isAssignedRegDep()) {
if (!LiveRegDefs[I->getReg()])
++NumLiveRegs;
// This becomes the nearest def. Note that an earlier def may still be
// pending if this is a two-address node.
LiveRegDefs[I->getReg()] = SU;
if (!LiveRegDefs[I->getReg()]) {
++NumLiveRegs;
}
if (LiveRegGens[I->getReg()] == NULL ||
I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight())
LiveRegGens[I->getReg()] = I->getSUnit();