mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-14 07:31:47 +00:00
Simplify some x86 format classes and remove some ambiguities in their application.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200608 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
f34dc1b514
commit
312eec7ecb
@ -850,7 +850,8 @@ multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
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}
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defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
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"ps", SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
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"ps", SSEPackedSingle>, TB, EVEX_4V, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
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"pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
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EVEX_CD8<64, CD8VF>;
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@ -1234,14 +1235,14 @@ let Constraints = "$src1 = $dst" in {
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defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
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"vmovaps", SSEPackedSingle>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
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"vmovapd", SSEPackedDouble>,
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PD, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
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"vmovups", SSEPackedSingle>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
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"vmovupd", SSEPackedDouble, 0>,
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PD, EVEX_V512, VEX_W,
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@ -1249,7 +1250,7 @@ defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
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def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
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"vmovaps\t{$src, $dst|$dst, $src}",
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[(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
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SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
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SSEPackedSingle>, EVEX, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
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def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
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"vmovapd\t{$src, $dst|$dst, $src}",
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[(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
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@ -1258,7 +1259,7 @@ def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$sr
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def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
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"vmovups\t{$src, $dst|$dst, $src}",
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[(store (v16f32 VR512:$src), addr:$dst)],
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SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
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SSEPackedSingle>, EVEX, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
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def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
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"vmovupd\t{$src, $dst|$dst, $src}",
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[(store (v8f64 VR512:$src), addr:$dst)],
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@ -1882,13 +1883,13 @@ multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
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defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
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VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
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VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
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VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
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VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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@ -2024,25 +2025,25 @@ multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
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def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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!strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
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EVEX_4V, TB;
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EVEX_4V;
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let mayLoad = 1 in {
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def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
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itins.rm, d>, EVEX_4V, TB;
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itins.rm, d>, EVEX_4V;
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def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86scalar_mop:$src2),
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!strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
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", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
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[(set RC:$dst, (OpNode RC:$src1,
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(vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
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itins.rm, d>, EVEX_4V, EVEX_B, TB;
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itins.rm, d>, EVEX_4V, EVEX_B;
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}
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}
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defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
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SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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SSE_ALU_ITINS_P.s, 1>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
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defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
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@ -2051,7 +2052,7 @@ defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
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defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
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SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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SSE_ALU_ITINS_P.s, 1>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
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defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
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SSE_ALU_ITINS_P.d, 1>,
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@ -2060,11 +2061,11 @@ defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
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defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
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SSE_ALU_ITINS_P.s, 1>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
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defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
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SSE_ALU_ITINS_P.s, 1>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
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defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
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@ -2077,10 +2078,10 @@ defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
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defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
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SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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SSE_ALU_ITINS_P.s, 0>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
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defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
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SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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SSE_ALU_ITINS_P.s, 0>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
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defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
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@ -2854,7 +2855,8 @@ defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, froun
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defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
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memopv4f64, f256mem, v8f64, v8f32,
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SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
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SSEPackedDouble>, EVEX_V512, TB,
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EVEX_CD8<32, CD8VH>;
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def : Pat<(v8f64 (extloadv8f32 addr:$src)),
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(VCVTPS2PDZrm addr:$src)>;
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@ -2872,7 +2874,8 @@ def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
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defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
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memopv8i64, i512mem, v16f32, v16i32,
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SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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SSEPackedSingle>, EVEX_V512, TB,
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EVEX_CD8<32, CD8VF>;
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defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
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memopv4i64, i256mem, v8f64, v8i32,
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@ -2891,7 +2894,7 @@ defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
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defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
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memopv16f32, f512mem, v16i32, v16f32,
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SSEPackedSingle>, EVEX_V512,
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SSEPackedSingle>, EVEX_V512, TB,
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EVEX_CD8<32, CD8VF>;
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// cvttps2udq (src, 0, mask-all-ones, sae-current)
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@ -2901,7 +2904,7 @@ def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
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defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
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memopv8f64, f512mem, v8i32, v8f64,
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SSEPackedDouble>, EVEX_V512, VEX_W,
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SSEPackedDouble>, EVEX_V512, TB, VEX_W,
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EVEX_CD8<64, CD8VF>;
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// cvttpd2udq (src, 0, mask-all-ones, sae-current)
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@ -2971,10 +2974,10 @@ def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
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defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
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memopv16f32, f512mem, SSEPackedSingle>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
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memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
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EVEX_V512, EVEX_CD8<64, CD8VF>;
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TB, EVEX_V512, EVEX_CD8<64, CD8VF>;
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def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
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(v16i32 immAllZerosV), (i16 -1), imm:$rc)),
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@ -3803,7 +3806,7 @@ multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
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}
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defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
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SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
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SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
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@ -151,7 +151,7 @@ class AdSize { bit hasAdSizePrefix = 1; }
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class REX_W { bit hasREX_WPrefix = 1; }
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class LOCK { bit hasLockPrefix = 1; }
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class REP { bit hasREPPrefix = 1; }
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class TB { Prefix OpPrefix = NoPrfx; Map OpMap = TB; }
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class TB { Map OpMap = TB; }
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class D8 { Map OpMap = D8; }
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class D9 { Map OpMap = D9; }
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class DA { Map OpMap = DA; }
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@ -160,21 +160,21 @@ class DC { Map OpMap = DC; }
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class DD { Map OpMap = DD; }
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class DE { Map OpMap = DE; }
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class DF { Map OpMap = DF; }
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class XD { Map OpMap = TB; Prefix OpPrefix = XD; }
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class XS { Map OpMap = TB; Prefix OpPrefix = XS; }
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class T8 { Map OpMap = T8; }
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class TA { Map OpMap = TA; }
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class A6 { Map OpMap = A6; }
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class A7 { Map OpMap = A7; }
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class T8XD { Map OpMap = T8; Prefix OpPrefix = XD; }
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class T8XS { Map OpMap = T8; Prefix OpPrefix = XS; }
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class TAXD { Map OpMap = TA; Prefix OpPrefix = XD; }
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class XOP8 { Map OpMap = XOP8; }
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class XOP9 { Map OpMap = XOP9; }
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class XOPA { Map OpMap = XOPA; }
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class PD { Map OpMap = TB; Prefix OpPrefix = PD; }
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class T8PD { Map OpMap = T8; Prefix OpPrefix = PD; }
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class TAPD { Map OpMap = TA; Prefix OpPrefix = PD; }
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class PD : TB { Prefix OpPrefix = PD; }
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class XD : TB { Prefix OpPrefix = XD; }
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class XS : TB { Prefix OpPrefix = XS; }
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class T8PD : T8 { Prefix OpPrefix = PD; }
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class T8XD : T8 { Prefix OpPrefix = XD; }
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class T8XS : T8 { Prefix OpPrefix = XS; }
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class TAPD : TA { Prefix OpPrefix = PD; }
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class TAXD : TA { Prefix OpPrefix = XD; }
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class VEX { bit hasVEXPrefix = 1; }
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class VEX_W { bit hasVEX_WPrefix = 1; }
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class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
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@ -699,7 +699,7 @@ class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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Requires<[HasAVX512]>;
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class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB,
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>,
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Requires<[HasAVX512]>;
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class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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@ -711,10 +711,10 @@ class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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Requires<[HasAVX512]>;
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class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
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: Ii8<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
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class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
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: I<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
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class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag>pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin>, T8PD,
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@ -523,28 +523,28 @@ let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
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let Predicates = [HasFSGSBase, In64BitMode] in {
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def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
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"rdfsbase{l}\t$dst",
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[(set GR32:$dst, (int_x86_rdfsbase_32))]>, TB, XS;
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[(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
|
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def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
|
||||
"rdfsbase{q}\t$dst",
|
||||
[(set GR64:$dst, (int_x86_rdfsbase_64))]>, TB, XS;
|
||||
[(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
|
||||
def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
|
||||
"rdgsbase{l}\t$dst",
|
||||
[(set GR32:$dst, (int_x86_rdgsbase_32))]>, TB, XS;
|
||||
[(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
|
||||
def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
|
||||
"rdgsbase{q}\t$dst",
|
||||
[(set GR64:$dst, (int_x86_rdgsbase_64))]>, TB, XS;
|
||||
[(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
|
||||
def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
|
||||
"wrfsbase{l}\t$src",
|
||||
[(int_x86_wrfsbase_32 GR32:$src)]>, TB, XS;
|
||||
[(int_x86_wrfsbase_32 GR32:$src)]>, XS;
|
||||
def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
|
||||
"wrfsbase{q}\t$src",
|
||||
[(int_x86_wrfsbase_64 GR64:$src)]>, TB, XS;
|
||||
[(int_x86_wrfsbase_64 GR64:$src)]>, XS;
|
||||
def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
|
||||
"wrgsbase{l}\t$src",
|
||||
[(int_x86_wrgsbase_32 GR32:$src)]>, TB, XS;
|
||||
[(int_x86_wrgsbase_32 GR32:$src)]>, XS;
|
||||
def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
|
||||
"wrgsbase{q}\t$src",
|
||||
[(int_x86_wrgsbase_64 GR64:$src)]>, TB, XS;
|
||||
[(int_x86_wrgsbase_64 GR64:$src)]>, XS;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
Loading…
Reference in New Issue
Block a user