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AArch64: don't create instructions that write to xzr/wzr twice.

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These are unpredictable even on AArch64.

Patch by Yichao Yu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266206 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2016-04-13 16:25:39 +00:00
parent 075abcbd06
commit 31cadd791a
2 changed files with 11 additions and 3 deletions
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8
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
View File

@ -93,6 +93,12 @@ bool AArch64DeadRegisterDefinitions::processMachineBasicBlock(
DEBUG(dbgs() << " Ignoring, operand is frame index\n"); DEBUG(dbgs() << " Ignoring, operand is frame index\n");
continue; continue;
} }
if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {
// It is not allowed to write to the same register (not even the zero
// register) twice in a single instruction.
DEBUG(dbgs() << " Ignoring, XZR or WZR already used by the instruction\n");
continue;
}
for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) { for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i); MachineOperand &MO = MI.getOperand(i);
if (MO.isReg() && MO.isDead() && MO.isDef()) { if (MO.isReg() && MO.isDead() && MO.isDef()) {
@ -128,6 +134,8 @@ bool AArch64DeadRegisterDefinitions::processMachineBasicBlock(
MO.setReg(NewReg); MO.setReg(NewReg);
DEBUG(MI.print(dbgs())); DEBUG(MI.print(dbgs()));
++NumDeadDefsReplaced; ++NumDeadDefsReplaced;
// Only replace one dead register, see check for zero register above.
break;
} }
} }
} }

6
test/CodeGen/AArch64/arm64-atomic-128.ll
View File

@ -190,7 +190,7 @@ define void @atomic_store_seq_cst(i128 %in, i128* %p) {
; CHECK-LABEL: atomic_store_seq_cst: ; CHECK-LABEL: atomic_store_seq_cst:
; CHECK-NOT: dmb ; CHECK-NOT: dmb
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]: ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp xzr, xzr, [x2] ; CHECK: ldaxp xzr, [[IGNORED:x[0-9]+]], [x2]
; CHECK: stlxp [[SUCCESS:w[0-9]+]], x0, x1, [x2] ; CHECK: stlxp [[SUCCESS:w[0-9]+]], x0, x1, [x2]
; CHECK: cbnz [[SUCCESS]], [[LABEL]] ; CHECK: cbnz [[SUCCESS]], [[LABEL]]
; CHECK-NOT: dmb ; CHECK-NOT: dmb
@ -202,7 +202,7 @@ define void @atomic_store_release(i128 %in, i128* %p) {
; CHECK-LABEL: atomic_store_release: ; CHECK-LABEL: atomic_store_release:
; CHECK-NOT: dmb ; CHECK-NOT: dmb
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]: ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldxp xzr, xzr, [x2] ; CHECK: ldxp xzr, [[IGNORED:x[0-9]+]], [x2]
; CHECK: stlxp [[SUCCESS:w[0-9]+]], x0, x1, [x2] ; CHECK: stlxp [[SUCCESS:w[0-9]+]], x0, x1, [x2]
; CHECK: cbnz [[SUCCESS]], [[LABEL]] ; CHECK: cbnz [[SUCCESS]], [[LABEL]]
; CHECK-NOT: dmb ; CHECK-NOT: dmb
@ -214,7 +214,7 @@ define void @atomic_store_relaxed(i128 %in, i128* %p) {
; CHECK-LABEL: atomic_store_relaxed: ; CHECK-LABEL: atomic_store_relaxed:
; CHECK-NOT: dmb ; CHECK-NOT: dmb
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]: ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldxp xzr, xzr, [x2] ; CHECK: ldxp xzr, [[IGNORED:x[0-9]+]], [x2]
; CHECK: stxp [[SUCCESS:w[0-9]+]], x0, x1, [x2] ; CHECK: stxp [[SUCCESS:w[0-9]+]], x0, x1, [x2]
; CHECK: cbnz [[SUCCESS]], [[LABEL]] ; CHECK: cbnz [[SUCCESS]], [[LABEL]]
; CHECK-NOT: dmb ; CHECK-NOT: dmb