[mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6

Summary:
Adds MIPS32r6/MIPS64r6 and checks the compatibility requirements for these
processors.

I've also included comments to describe removed and re-encoded instructions,
along with placeholder def's for the new instructions but there are no
functional changes to codegen at this point.

Reviewers: jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3622

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208399 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/Mips.td

@@ -98,6 +98,11 @@ def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
                                 "Mips32r2", "Mips32r2 ISA Support",
                                 [FeatureMips32, FeatureSEInReg, FeatureSwap,
                                  FeatureFPIdx]>;
+def FeatureMips32r6    : SubtargetFeature<"mips32r6", "MipsArchVersion",
+                                "Mips32r6",
+                                "Mips32r6 ISA Support [experimental]",
+                                [FeatureMips32r2, FeatureFP64Bit,
+                                 FeatureNaN2008]>;
 // FIXME: Need to check whether FPIdx belongs in the MIPS-III or MIPS-IV Implies
 //        list but for now it doesn't matter since FPIdx isn't actually attached
 //        to any instructions.
@@ -116,6 +121,10 @@ def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
 def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
                                 "Mips64r2", "Mips64r2 ISA Support",
                                 [FeatureMips64, FeatureMips32r2]>;
+def FeatureMips64r6    : SubtargetFeature<"mips64r6", "MipsArchVersion",
+                                "Mips64r6",
+                                "Mips64r6 ISA Support [experimental]",
+                                [FeatureMips64r2, FeatureNaN2008]>;
 
 def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
                                       "Mips16 mode">;
@@ -144,12 +153,14 @@ def : Proc<"mips1", [FeatureMips1, FeatureO32]>;
 def : Proc<"mips2", [FeatureMips2, FeatureO32]>;
 def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
 def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
+def : Proc<"mips32r6", [FeatureMips32r6, FeatureO32]>;
 
 def : Proc<"mips3", [FeatureMips3, FeatureN64]>;
 def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
 def : Proc<"mips5", [FeatureMips5, FeatureN64]>;
 def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
 def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
+def : Proc<"mips64r6", [FeatureMips64r6, FeatureN64]>;
 def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
 def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
 

lib/Target/Mips/Mips32r6InstrInfo.td

@@ -0,0 +1,123 @@
+//=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes Mips32r6 instructions.
+//
+//===----------------------------------------------------------------------===//
+
+// Notes about removals/changes from MIPS32r6:
+// Unclear: ssnop
+// Reencoded: cache, pref
+// Reencoded: clo, clz
+// Reencoded: jr -> jalr
+// Reencoded: jr.hb -> jalr.hb
+// Reencoded: ldc2
+// Reencoded: ll, sc
+// Reencoded: lwc2
+// Reencoded: sdbbp
+// Reencoded: sdc2
+// Reencoded: swc2
+// Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
+// Removed: addi
+// Removed: bc1any2, bc1any4
+// Removed: bc2[ft]
+// Removed: bc2f, bc2t
+// Removed: bc[12][ft]l, bgezl, bgtzl, bgtzl, blezl, bltzall, bltzl, bnel, bgezall,
+// Removed: beql
+// Removed: bgezal
+// Removed: bltzal
+// Removed: c.cond.fmt, bc1[ft]
+// Removed: div, divu
+// Removed: jalx
+// Removed: ldxc1
+// Removed: luxc1
+// Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
+// Removed: lwxc1
+// Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
+// Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
+// Removed: movf, movt
+// Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
+// Removed: movn, movz
+// Removed: mult, multu
+// Removed: prefx
+// Removed: sdxc1
+// Removed: suxc1
+// Removed: swxc1
+// Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
+// Rencoded: [ls][wd]c2
+
+def ADDIUPC;
+def ALIGN; // Known as as BALIGN in DSP ASE
+def ALUIPC;
+def AUI;
+def AUIPC;
+def BALC;
+def BC1EQZ;
+def BC1NEZ;
+def BC2EQZ;
+def BC2NEZ;
+def BC;
+def BEQC;
+def BEQZALC;
+def BEQZC;
+def BGEC;  // Also aliased to blec with operands swapped
+def BGEUC; // Also aliased to bleuc with operands swapped
+def BGEZALC;
+def BGEZC;
+def BGTZALC;
+def BGTZC;
+def BITSWAP; // Known as BITREV in DSP ASE
+def BLEZALC;
+def BLEZC;
+def BLTC; // Also aliased to bgtc with operands swapped
+def BLTUC; // Also aliased to bgtuc with operands swapped
+def BLTZALC;
+def BLTZC;
+def BNEC;
+def BNEZALC;
+def BNEZC;
+def BNVC;
+def BOVC;
+def CLASS_D;
+def CLASS_S;
+def CMP_CC_D;
+def CMP_CC_S;
+def DIV;   // Not to be confused with the old div
+def DIVU;  // Not to be confused with the old div
+def JIALC;
+def JIC;
+// def LSA; // See MSA
+def LWPC;
+def LWUPC;
+def MADDF;
+def MAXA_D;
+def MAXA_S;
+def MAX_D;
+def MAX_S;
+def MINA_D;
+def MINA_S;
+def MIN_D;
+def MOD;
+def MODU;
+def MSUBF;
+def MUH;
+def MUHU;
+def MUL_R6; // Not to be confused with the old mul
+def MULU;
+def NAL; // BAL with rd=0
+def RINT_D;
+def RINT_S;
+def SELEQZ;
+def SELEQZ_D;
+def SELEQZ_S;
+def SELNEZ;
+def SELNEZ_D;
+def SELNEZ_S;
+def SEL_D;
+def SEL_S;

lib/Target/Mips/Mips64r6InstrInfo.td

@@ -0,0 +1,36 @@
+//=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes Mips64r6 instructions.
+//
+//===----------------------------------------------------------------------===//
+
+// Notes about removals/changes from MIPS32r6:
+// Reencoded: dclo, dclz
+// Reencoded: lld, scd
+// Removed: daddi
+// Removed: ddiv, ddivu, dmult, dmultu
+// Removed: div, divu
+// Removed: ldl, ldr, ldle, ldre, sdl, sdr, sdle, sdre
+
+def DAHI;
+def DALIGN;
+def DATI;
+def DAUI;
+def DBITSWAP;
+def DDIV;
+def DDIVU;
+// def DLSA; // See MSA
+def DMOD;
+def DMODU;
+def DMUH;
+def DMUHU;
+def DMUL_R6; // Not to be confused with the old mul
+def DMULU;
+def LDPC;

lib/Target/Mips/MipsInstrInfo.td

@@ -1522,6 +1522,9 @@ include "MipsInstrFPU.td"
 include "Mips64InstrInfo.td"
 include "MipsCondMov.td"
 
+include "Mips32r6InstrInfo.td"
+include "Mips64r6InstrInfo.td"
+
 //
 // Mips16
 

lib/Target/Mips/MipsSubtarget.cpp

@@ -137,6 +137,15 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
                        "See -mattr=+fp64.",
                        false);
 
+  if (hasMips32r6()) {
+    StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
+
+    assert(isFP64bit());
+    assert(isNaN2008());
+    if (hasDSP())
+      report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
+  }
+
   // Is the target system Linux ?
   if (TT.find("linux") == std::string::npos)
     IsLinux = false;

lib/Target/Mips/MipsSubtarget.h

@@ -37,8 +37,10 @@ public:
   };
 
 protected:
-  enum MipsArchEnum { Mips1, Mips2, Mips32, Mips32r2, Mips3, Mips4, Mips5,
-                      Mips64, Mips64r2 };
+  enum MipsArchEnum {
+    Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
+    Mips64r2, Mips64r6
+  };
 
   // Mips architecture version
   MipsArchEnum MipsArchVersion;
@@ -156,8 +158,11 @@ public:
   bool hasMips32() const { return MipsArchVersion >= Mips32; }
   bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
                                    MipsArchVersion == Mips64r2; }
+  bool hasMips32r6() const { return MipsArchVersion == Mips32r6 ||
+                                   MipsArchVersion == Mips64r6; }
   bool hasMips64() const { return MipsArchVersion >= Mips64; }
   bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
+  bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
 
   bool hasCnMips() const { return HasCnMips; }
 

test/CodeGen/Mips/mips32r6/compatibility.ll

@@ -0,0 +1,9 @@
+; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s
+; RUN: not llc -march=mipsel -mcpu=mips32r6 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s
+
+; CHECK: foo:
+; DSP: MIPS32r6 is not compatible with the DSP ASE
+
+define void @foo() nounwind {
+  ret void
+}

test/CodeGen/Mips/mips64r6/compatibility.ll

@@ -0,0 +1,9 @@
+; RUN: llc -march=mipsel -mcpu=mips64r6 < %s | FileCheck %s
+; RUN: not llc -march=mipsel -mcpu=mips64r6 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s
+
+; CHECK: foo:
+; DSP: MIPS64r6 is not compatible with the DSP ASE
+
+define void @foo() nounwind {
+  ret void
+}