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[Power9] Exploit vector integer extend instructions
This patch adds build vector patterns to exploit the vector integer extend instructions: vextsb2w - Vector Extend Sign Byte To Word vextsb2d - Vector Extend Sign Byte To Doubleword vextsh2w - Vector Extend Sign Halfword To Word vextsh2d - Vector Extend Sign Halfword To Doubleword vextsw2d - Vector Extend Sign Word To Doubleword Differential Revision: https://reviews.llvm.org/D33510 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304992 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zaara Syeda
parent
06abfee96e
commit
32a3852f3c
@ -2717,6 +2717,40 @@ def DblToFlt {
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dag B0 = (f32 (fpround (f64 (extractelt v2f64:$B, 0))));
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dag B1 = (f32 (fpround (f64 (extractelt v2f64:$B, 1))));
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}
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def ByteToWord {
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dag A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 0)), i8));
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dag A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 4)), i8));
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dag A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 8)), i8));
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dag A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 12)), i8));
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}
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def ByteToDWord {
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dag A0 = (i64 (sext_inreg
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(i64 (anyext (i32 (vector_extract v16i8:$A, 0)))), i8));
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dag A1 = (i64 (sext_inreg
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(i64 (anyext (i32 (vector_extract v16i8:$A, 8)))), i8));
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}
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def HWordToWord {
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dag A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 0)), i16));
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dag A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 2)), i16));
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dag A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 4)), i16));
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dag A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 6)), i16));
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}
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def HWordToDWord {
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dag A0 = (i64 (sext_inreg
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(i64 (anyext (i32 (vector_extract v8i16:$A, 0)))), i16));
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dag A1 = (i64 (sext_inreg
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(i64 (anyext (i32 (vector_extract v8i16:$A, 4)))), i16));
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}
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def WordToDWord {
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dag A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 0))));
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dag A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 2))));
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}
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def FltToIntLoad {
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dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (extloadf32 xoaddr:$A)))));
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}
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@ -2969,4 +3003,21 @@ let AddedComplexity = 400 in {
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(VMRGOW (COPY_TO_REGCLASS (MTVSRDD AnyExts.D, AnyExts.B), VSRC),
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(COPY_TO_REGCLASS (MTVSRDD AnyExts.C, AnyExts.A), VSRC))>;
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}
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// P9 Altivec instructions that can be used to build vectors.
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// Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete
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// with complexities of existing build vector patterns in this file.
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let Predicates = [HasP9Altivec] in {
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def : Pat<(v2i64 (build_vector WordToDWord.A0, WordToDWord.A1)),
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(v2i64 (VEXTSW2D $A))>;
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def : Pat<(v2i64 (build_vector HWordToDWord.A0, HWordToDWord.A1)),
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(v2i64 (VEXTSH2D $A))>;
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def : Pat<(v4i32 (build_vector HWordToWord.A0, HWordToWord.A1,
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HWordToWord.A2, HWordToWord.A3)),
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(v4i32 (VEXTSH2W $A))>;
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def : Pat<(v4i32 (build_vector ByteToWord.A0, ByteToWord.A1,
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ByteToWord.A2, ByteToWord.A3)),
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(v4i32 (VEXTSB2W $A))>;
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def : Pat<(v2i64 (build_vector ByteToDWord.A0, ByteToDWord.A1)),
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(v2i64 (VEXTSB2D $A))>;
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}
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}
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90
test/CodeGen/PowerPC/vec_int_ext.ll
Normal file
90
test/CodeGen/PowerPC/vec_int_ext.ll
Normal file
@ -0,0 +1,90 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck %s -check-prefix=PWR9
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target triple = "powerpc64le-unknown-linux-gnu"
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define <4 x i32> @vextsb2w(<16 x i8> %a) {
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; PWR9-LABEL: vextsb2w:
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; PWR9: # BB#0: # %entry
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; PWR9-NEXT: vextsb2w 2, 2
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; PWR9-NEXT: blr
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entry:
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%vecext = extractelement <16 x i8> %a, i32 0
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%conv = sext i8 %vecext to i32
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%vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
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%vecext1 = extractelement <16 x i8> %a, i32 4
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%conv2 = sext i8 %vecext1 to i32
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%vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
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%vecext4 = extractelement <16 x i8> %a, i32 8
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%conv5 = sext i8 %vecext4 to i32
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%vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
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%vecext7 = extractelement <16 x i8> %a, i32 12
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%conv8 = sext i8 %vecext7 to i32
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%vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
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ret <4 x i32> %vecinit9
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}
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define <2 x i64> @vextsb2d(<16 x i8> %a) {
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; PWR9-LABEL: vextsb2d:
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; PWR9: # BB#0: # %entry
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; PWR9-NEXT: vextsb2d 2, 2
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; PWR9-NEXT: blr
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entry:
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%vecext = extractelement <16 x i8> %a, i32 0
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%conv = sext i8 %vecext to i64
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%vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
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%vecext1 = extractelement <16 x i8> %a, i32 8
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%conv2 = sext i8 %vecext1 to i64
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%vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
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ret <2 x i64> %vecinit3
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}
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define <4 x i32> @vextsh2w(<8 x i16> %a) {
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; PWR9-LABEL: vextsh2w:
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; PWR9: # BB#0: # %entry
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; PWR9-NEXT: vextsh2w 2, 2
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; PWR9-NEXT: blr
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entry:
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%vecext = extractelement <8 x i16> %a, i32 0
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%conv = sext i16 %vecext to i32
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%vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
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%vecext1 = extractelement <8 x i16> %a, i32 2
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%conv2 = sext i16 %vecext1 to i32
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%vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
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%vecext4 = extractelement <8 x i16> %a, i32 4
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%conv5 = sext i16 %vecext4 to i32
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%vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
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%vecext7 = extractelement <8 x i16> %a, i32 6
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%conv8 = sext i16 %vecext7 to i32
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%vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
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ret <4 x i32> %vecinit9
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}
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define <2 x i64> @vextsh2d(<8 x i16> %a) {
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; PWR9-LABEL: vextsh2d:
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; PWR9: # BB#0: # %entry
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; PWR9-NEXT: vextsh2d 2, 2
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; PWR9-NEXT: blr
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entry:
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%vecext = extractelement <8 x i16> %a, i32 0
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%conv = sext i16 %vecext to i64
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%vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
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%vecext1 = extractelement <8 x i16> %a, i32 4
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%conv2 = sext i16 %vecext1 to i64
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%vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
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ret <2 x i64> %vecinit3
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}
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define <2 x i64> @vextsw2d(<4 x i32> %a) {
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; PWR9-LABEL: vextsw2d:
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; PWR9: # BB#0: # %entry
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; PWR9-NEXT: vextsw2d 2, 2
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; PWR9-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 0
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%conv = sext i32 %vecext to i64
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%vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
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%vecext1 = extractelement <4 x i32> %a, i32 2
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%conv2 = sext i32 %vecext1 to i64
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%vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
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ret <2 x i64> %vecinit3
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}
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