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[FastISel][AArch64] Factor out add with immediate emission into a helper function. NFC.

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Simplify add with immediate emission by factoring it out into a helper function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219830 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2014-10-15 18:58:02 +00:00
parent ad04f5db82
commit 32c5fde3f1
1 changed files with 28 additions and 13 deletions
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41
lib/Target/AArch64/AArch64FastISel.cpp
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@ -188,6 +188,7 @@ private:
unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
bool SetFlags = false, bool WantResult = true,
bool IsZExt = false);
unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
bool SetFlags = false, bool WantResult = true,
bool IsZExt = false);
@ -1002,20 +1003,10 @@ bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
// reg+offset into a register.
if (ImmediateOffsetNeedsLowering) {
unsigned ResultReg;
if (Addr.getReg()) {
if (Addr.getReg())
// Try to fold the immediate into the add instruction.
if (Offset < 0)
ResultReg = emitAddSub_ri(/*UseAdd=*/false, MVT::i64, Addr.getReg(),
/*IsKill=*/false, -Offset);
else
ResultReg = emitAddSub_ri(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
/*IsKill=*/false, Offset);
if (!ResultReg) {
unsigned ImmReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
ResultReg = emitAddSub_rr(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
/*IsKill=*/false, ImmReg, /*IsKill=*/true);
}
} else
ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), /*IsKill=*/false, Offset);
else
ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
if (!ResultReg)
@ -1442,6 +1433,30 @@ unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
IsZExt);
}
/// \brief This method is a wrapper to simplify add emission.
///
/// First try to emit an add with an immediate operand using emitAddSub_ri. If
/// that fails, then try to materialize the immediate into a register and use
/// emitAddSub_rr instead.
unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill,
int64_t Imm) {
unsigned ResultReg;
if (Imm < 0)
ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm);
else
ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm);
if (ResultReg)
return ResultReg;
unsigned CReg = fastEmit_i(VT, VT, ISD::Constant, Imm);
if (!CReg)
return 0;
ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true);
return ResultReg;
}
unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
bool SetFlags, bool WantResult, bool IsZExt) {
return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult,