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[FastISel][AArch64] Also allow folding of sign-/zero-extend and arithmetic

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shift-right for booleans (i1).

Arithmetic shift-right immediate with sign-/zero-extensions also works for
boolean values.  Update the assert and the test cases to reflect that fact.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222272 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2014-11-18 22:41:49 +00:00
parent 5e3288f85b
commit 32dc2de667
2 changed files with 52 additions and 2 deletions
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5
lib/Target/AArch64/AArch64FastISel.cpp
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@ -4117,8 +4117,9 @@ unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
bool IsZExt) {
assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
"Unexpected source/return type pair.");
assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
SrcVT == MVT::i64) && "Unexpected source value type.");
assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
"Unexpected source value type.");
assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
RetVT == MVT::i64) && "Unexpected return value type.");

49
test/CodeGen/AArch64/fast-isel-shift.ll
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@ -1,5 +1,54 @@
; RUN: llc -fast-isel -fast-isel-abort -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: asr_zext_i1_i16
; CHECK: uxth {{w[0-9]*}}, wzr
define zeroext i16 @asr_zext_i1_i16(i1 %b) {
%1 = zext i1 %b to i16
%2 = ashr i16 %1, 1
ret i16 %2
}
; CHECK-LABEL: asr_sext_i1_i16
; CHECK: sbfx [[REG1:w[0-9]+]], {{w[0-9]*}}, #0, #1
; CHECK-NEXT: sxth {{w[0-9]*}}, [[REG1]]
define signext i16 @asr_sext_i1_i16(i1 %b) {
%1 = sext i1 %b to i16
%2 = ashr i16 %1, 1
ret i16 %2
}
; CHECK-LABEL: asr_zext_i1_i32
; CHECK: mov {{w[0-9]*}}, wzr
define i32 @asr_zext_i1_i32(i1 %b) {
%1 = zext i1 %b to i32
%2 = ashr i32 %1, 1
ret i32 %2
}
; CHECK-LABEL: asr_sext_i1_i32
; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #0, #1
define i32 @asr_sext_i1_i32(i1 %b) {
%1 = sext i1 %b to i32
%2 = ashr i32 %1, 1
ret i32 %2
}
; CHECK-LABEL: asr_zext_i1_i64
; CHECK: mov {{x[0-9]*}}, xzr
define i64 @asr_zext_i1_i64(i1 %b) {
%1 = zext i1 %b to i64
%2 = ashr i64 %1, 1
ret i64 %2
}
; CHECK-LABEL: asr_sext_i1_i64
; CHECK: sbfx {{x[0-9]*}}, {{x[0-9]*}}, #0, #1
define i64 @asr_sext_i1_i64(i1 %b) {
%1 = sext i1 %b to i64
%2 = ashr i64 %1, 1
ret i64 %2
}
; CHECK-LABEL: lsr_zext_i1_i16
; CHECK: uxth {{w[0-9]*}}, wzr
define zeroext i16 @lsr_zext_i1_i16(i1 %b) {