RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-02-22 14:05:03 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1)

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273885 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2016-06-27 15:08:22 +00:00
parent 4cc8cc2f69
commit 339dc3dc8f
3 changed files with 51 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
View File

@ -104,6 +104,7 @@ public:
void SelectConstant(SDNode *N);
void SelectConstantFP(SDNode *N);
void SelectAdd(SDNode *N);
void SelectBitcast(SDNode *N);
void SelectBitOp(SDNode *N);
// XformMskToBitPosU5Imm - Returns the bit position which
@ -1165,6 +1166,22 @@ void HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
}
void HexagonDAGToDAGISel::SelectBitcast(SDNode *N) {
EVT SVT = N->getOperand(0).getValueType();
EVT DVT = N->getValueType(0);
if (!SVT.isVector() || !DVT.isVector() ||
SVT.getVectorElementType() == MVT::i1 ||
DVT.getVectorElementType() == MVT::i1 ||
SVT.getSizeInBits() != DVT.getSizeInBits()) {
SelectCode(N);
return;
}
CurDAG->ReplaceAllUsesOfValueWith(SDValue(N,0), N->getOperand(0));
CurDAG->RemoveDeadNode(N);
}
void HexagonDAGToDAGISel::Select(SDNode *N) {
if (N->isMachineOpcode()) {
N->setNodeId(-1);
@ -1188,6 +1205,10 @@ void HexagonDAGToDAGISel::Select(SDNode *N) {
SelectAdd(N);
return;
case ISD::BITCAST:
SelectBitcast(N);
return;
case ISD::SHL:
SelectSHL(N);
return;

55
lib/Target/Hexagon/HexagonInstrInfoVector.td
View File

@ -35,61 +35,12 @@ multiclass bitconvert_64<ValueType a, ValueType b> {
(a DoubleRegs:$src)>;
}
multiclass bitconvert_vec<ValueType a, ValueType b> {
def : Pat <(b (bitconvert (a VectorRegs:$src))),
(b VectorRegs:$src)>;
def : Pat <(a (bitconvert (b VectorRegs:$src))),
(a VectorRegs:$src)>;
}
multiclass bitconvert_dblvec<ValueType a, ValueType b> {
def : Pat <(b (bitconvert (a VecDblRegs:$src))),
(b VecDblRegs:$src)>;
def : Pat <(a (bitconvert (b VecDblRegs:$src))),
(a VecDblRegs:$src)>;
}
multiclass bitconvert_predvec<ValueType a, ValueType b> {
def : Pat <(b (bitconvert (a VecPredRegs:$src))),
(b VectorRegs:$src)>;
def : Pat <(a (bitconvert (b VectorRegs:$src))),
(a VecPredRegs:$src)>;
}
multiclass bitconvert_dblvec128B<ValueType a, ValueType b> {
def : Pat <(b (bitconvert (a VecDblRegs128B:$src))),
(b VecDblRegs128B:$src)>;
def : Pat <(a (bitconvert (b VecDblRegs128B:$src))),
(a VecDblRegs128B:$src)>;
}
// Bit convert vector types.
defm : bitconvert_32<v4i8, i32>;
// Bit convert vector types to integers.
defm : bitconvert_32<v4i8, i32>;
defm : bitconvert_32<v2i16, i32>;
defm : bitconvert_32<v2i16, v4i8>;
defm : bitconvert_64<v8i8, i64>;
defm : bitconvert_64<v8i8, i64>;
defm : bitconvert_64<v4i16, i64>;
defm : bitconvert_64<v2i32, i64>;
defm : bitconvert_64<v8i8, v4i16>;
defm : bitconvert_64<v8i8, v2i32>;
defm : bitconvert_64<v4i16, v2i32>;
defm : bitconvert_vec<v64i8, v16i32>;
defm : bitconvert_vec<v8i64 , v16i32>;
defm : bitconvert_vec<v32i16, v16i32>;
defm : bitconvert_dblvec<v16i64, v128i8>;
defm : bitconvert_dblvec<v32i32, v128i8>;
defm : bitconvert_dblvec<v64i16, v128i8>;
defm : bitconvert_dblvec128B<v64i32, v128i16>;
defm : bitconvert_dblvec128B<v256i8, v128i16>;
defm : bitconvert_dblvec128B<v32i64, v128i16>;
defm : bitconvert_dblvec128B<v64i32, v256i8>;
defm : bitconvert_dblvec128B<v32i64, v256i8>;
defm : bitconvert_dblvec128B<v128i16, v256i8>;
// Vector shift support. Vector shifting in Hexagon is rather different
// from internal representation of LLVM.

27
test/CodeGen/Hexagon/bitconvert-vector.ll Normal file
View File

@ -0,0 +1,27 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; This testcase would fail on a bitcast from v64i16 to v32i32. Check that
; is compiles without errors.
; CHECK: valign
; CHECK: vshuff
target triple = "hexagon"
declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #0
declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #0
declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0
define void @fred() #1 {
entry:
%t0 = bitcast <64 x i16> zeroinitializer to <32 x i32>
%t1 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> %t0, <32 x i32> undef, i32 2)
%t2 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> undef, <32 x i32> %t1, i32 -2)
%t3 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %t2)
store <64 x i16> zeroinitializer, <64 x i16>* undef, align 128
store <32 x i32> %t3, <32 x i32>* undef, align 128
unreachable
}
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }