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[AVX512] Extended avx512_binop_rm for AVX512VL subsets.
Added avx512_binop_rm_vl multiclass for VL subset Added encoding tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219390 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Khasanov
parent
5b1b9844e7
commit
340b5b9ad7
@ -2537,6 +2537,21 @@ multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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}
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}
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multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
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AVX512VLVectorVTInfo VTInfo, OpndItins itins,
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Predicate prd, bit IsCommutable = 0> {
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let Predicates = [prd] in
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defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
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IsCommutable>, EVEX_V512;
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let Predicates = [prd, HasVLX] in {
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defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
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IsCommutable>, EVEX_V256;
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defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
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IsCommutable>, EVEX_V128;
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}
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}
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multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
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ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
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PatFrag memop_frag, X86MemOperand x86memop,
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@ -2594,20 +2609,20 @@ multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
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}
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}
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defm VPADDDZ : avx512_binop_rm<0xFE, "vpadd", add, v16i32_info,
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SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPADDD : avx512_binop_rm_vl<0xFE, "vpadd", add, avx512vl_i32_info,
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SSE_INTALU_ITINS_P, HasAVX512, 1>, EVEX_CD8<32, CD8VF>;
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defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsub", sub, v16i32_info,
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SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPSUBD : avx512_binop_rm_vl<0xFA, "vpsub", sub, avx512vl_i32_info,
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SSE_INTALU_ITINS_P, HasAVX512, 0>, EVEX_CD8<32, CD8VF>;
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defm VPMULLDZ : avx512_binop_rm<0x40, "vpmull", mul, v16i32_info,
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SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPMULLD : avx512_binop_rm_vl<0x40, "vpmull", mul, avx512vl_i32_info,
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SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD, EVEX_CD8<32, CD8VF>;
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defm VPADDQZ : avx512_binop_rm<0xD4, "vpadd", add, v8i64_info,
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SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
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defm VPADDQ : avx512_binop_rm_vl<0xD4, "vpadd", add, avx512vl_i64_info,
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SSE_INTALU_ITINS_P, HasAVX512, 1>, EVEX_CD8<64, CD8VF>, VEX_W;
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defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsub", sub, v8i64_info,
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SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPSUBQ : avx512_binop_rm_vl<0xFB, "vpsub", sub, avx512vl_i64_info,
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SSE_INTALU_ITINS_P, HasAVX512, 0>, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
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memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
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@ -2628,33 +2643,33 @@ def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
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(v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
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(VPMULDQZrr VR512:$src1, VR512:$src2)>;
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defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v16i32_info,
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SSE_INTALU_ITINS_P, 1>,
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T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v8i64_info,
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SSE_INTALU_ITINS_P, 0>,
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T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPMAXUD : avx512_binop_rm_vl<0x3F, "vpmaxu", X86umax, avx512vl_i32_info,
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SSE_INTALU_ITINS_P, HasAVX512, 1>,
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T8PD, EVEX_CD8<32, CD8VF>;
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defm VPMAXUQ : avx512_binop_rm_vl<0x3F, "vpmaxu", X86umax, avx512vl_i64_info,
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SSE_INTALU_ITINS_P, HasAVX512, 0>,
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T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v16i32_info,
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SSE_INTALU_ITINS_P, 1>,
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T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v8i64_info,
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SSE_INTALU_ITINS_P, 0>,
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T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPMAXSD : avx512_binop_rm_vl<0x3D, "vpmaxs", X86smax, avx512vl_i32_info,
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SSE_INTALU_ITINS_P, HasAVX512, 1>,
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T8PD, EVEX_CD8<32, CD8VF>;
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defm VPMAXSQ : avx512_binop_rm_vl<0x3D, "vpmaxs", X86smax, avx512vl_i64_info,
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SSE_INTALU_ITINS_P, HasAVX512, 0>,
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T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v16i32_info,
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SSE_INTALU_ITINS_P, 1>,
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T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v8i64_info,
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SSE_INTALU_ITINS_P, 0>,
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T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPMINUD : avx512_binop_rm_vl<0x3B, "vpminu", X86umin, avx512vl_i32_info,
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SSE_INTALU_ITINS_P, HasAVX512, 1>,
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T8PD, EVEX_CD8<32, CD8VF>;
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defm VPMINUQ : avx512_binop_rm_vl<0x3B, "vpminu", X86umin, avx512vl_i64_info,
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SSE_INTALU_ITINS_P, HasAVX512, 0>,
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T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPMINSDZ : avx512_binop_rm<0x39, "vpmins", X86smin, v16i32_info,
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SSE_INTALU_ITINS_P, 1>,
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T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPMINSQZ : avx512_binop_rm<0x39, "vpmins", X86smin, v8i64_info,
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SSE_INTALU_ITINS_P, 0>,
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T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPMINSD : avx512_binop_rm_vl<0x39, "vpmins", X86smin, avx512vl_i32_info,
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SSE_INTALU_ITINS_P, HasAVX512, 1>,
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T8PD, EVEX_CD8<32, CD8VF>;
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defm VPMINSQ : avx512_binop_rm_vl<0x39, "vpmins", X86smin, avx512vl_i64_info,
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SSE_INTALU_ITINS_P, HasAVX512, 0>,
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T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
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def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
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(v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
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@ -2785,22 +2800,30 @@ def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
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// AVX-512 Logical Instructions
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//===----------------------------------------------------------------------===//
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defm VPANDDZ : avx512_binop_rm<0xDB, "vpand", and, v16i32_info, SSE_BIT_ITINS_P, 1>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPANDQZ : avx512_binop_rm<0xDB, "vpand", and, v8i64_info, SSE_BIT_ITINS_P, 1>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPORDZ : avx512_binop_rm<0xEB, "vpor", or, v16i32_info, SSE_BIT_ITINS_P, 1>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPORQZ : avx512_binop_rm<0xEB, "vpor", or, v8i64_info, SSE_BIT_ITINS_P, 1>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPXORDZ : avx512_binop_rm<0xEF, "vpxor", xor, v16i32_info, SSE_BIT_ITINS_P, 1>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPXORQZ : avx512_binop_rm<0xEF, "vpxor", xor, v8i64_info, SSE_BIT_ITINS_P, 1>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v16i32_info,
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SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v8i64_info,
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SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPANDD : avx512_binop_rm_vl<0xDB, "vpand", and, avx512vl_i32_info,
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SSE_BIT_ITINS_P, HasAVX512, 1>,
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EVEX_CD8<32, CD8VF>;
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defm VPANDQ : avx512_binop_rm_vl<0xDB, "vpand", and, avx512vl_i64_info,
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SSE_BIT_ITINS_P, HasAVX512, 1>,
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VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPORD : avx512_binop_rm_vl<0xEB, "vpor", or, avx512vl_i32_info,
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SSE_BIT_ITINS_P, HasAVX512, 1>,
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EVEX_CD8<32, CD8VF>;
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defm VPORQ : avx512_binop_rm_vl<0xEB, "vpor", or, avx512vl_i64_info,
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SSE_BIT_ITINS_P, HasAVX512, 1>,
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VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPXORD : avx512_binop_rm_vl<0xEF, "vpxor", xor, avx512vl_i32_info,
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SSE_BIT_ITINS_P, HasAVX512, 1>,
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EVEX_CD8<32, CD8VF>;
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defm VPXORQ : avx512_binop_rm_vl<0xEF, "vpxor", xor, avx512vl_i64_info,
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SSE_BIT_ITINS_P, HasAVX512, 1>,
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VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPANDND : avx512_binop_rm_vl<0xDF, "vpandn", X86andnp, avx512vl_i32_info,
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SSE_BIT_ITINS_P, HasAVX512, 0>,
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EVEX_CD8<32, CD8VF>;
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defm VPANDNQ : avx512_binop_rm_vl<0xDF, "vpandn", X86andnp, avx512vl_i64_info,
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SSE_BIT_ITINS_P, HasAVX512, 0>,
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VEX_W, EVEX_CD8<64, CD8VF>;
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//===----------------------------------------------------------------------===//
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// AVX-512 FP arithmetic
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File diff suppressed because it is too large
Load Diff
@ -219,6 +219,7 @@ static inline bool inheritsFrom(InstructionContext child,
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case IC_EVEX_OPSIZE_B:
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case IC_EVEX_OPSIZE_K_B:
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case IC_EVEX_OPSIZE_KZ:
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case IC_EVEX_OPSIZE_KZ_B:
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return false;
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case IC_EVEX_W_K:
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case IC_EVEX_W_XS_K:
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@ -238,11 +239,13 @@ static inline bool inheritsFrom(InstructionContext child,
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case IC_EVEX_W_XS_KZ:
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case IC_EVEX_W_XD_KZ:
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case IC_EVEX_W_OPSIZE_KZ:
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case IC_EVEX_W_OPSIZE_KZ_B:
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return false;
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case IC_EVEX_L_KZ:
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case IC_EVEX_L_XS_KZ:
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case IC_EVEX_L_XD_KZ:
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case IC_EVEX_L_OPSIZE_KZ:
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case IC_EVEX_L_OPSIZE_KZ_B:
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return false;
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case IC_EVEX_L_W_K:
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case IC_EVEX_L_W_XS_K:
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@ -254,6 +257,7 @@ static inline bool inheritsFrom(InstructionContext child,
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case IC_EVEX_L_W_XS_KZ:
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case IC_EVEX_L_W_XD_KZ:
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case IC_EVEX_L_W_OPSIZE_KZ:
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case IC_EVEX_L_W_OPSIZE_KZ_B:
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return false;
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case IC_EVEX_L2_K:
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case IC_EVEX_L2_B:
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