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Comments and cleaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121809 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -26,7 +26,6 @@ def imm_comp_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
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}]>;
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/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
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def imm0_7 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 8;
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@ -127,7 +126,6 @@ def t_addrmode_rrs1 : Operand<i32>,
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let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
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let ParserMatchClass = MemModeRegThumbAsmOperand;
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}
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def t_addrmode_rrs2 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
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let EncoderMethod = "getThumbAddrModeRegRegOpValue";
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@ -618,12 +616,12 @@ multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
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AddrMode am, InstrItinClass itin_r,
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InstrItinClass itin_i, string asm,
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PatFrag opnode> {
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def r :
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def r : // reg/reg
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T1pILdStEncode<reg_opc,
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(outs tGPR:$Rt), (ins AddrMode_r:$addr),
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am, itin_r, asm, "\t$Rt, $addr",
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[(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
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def i :
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def i : // reg/imm5
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T1pILdStEncodeImm<imm_opc, 1 /* Load */,
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(outs tGPR:$Rt), (ins AddrMode_i:$addr),
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am, itin_i, asm, "\t$Rt, $addr",
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@ -635,12 +633,12 @@ multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
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AddrMode am, InstrItinClass itin_r,
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InstrItinClass itin_i, string asm,
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PatFrag opnode> {
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def r :
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def r : // reg/reg
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T1pILdStEncode<reg_opc,
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(outs), (ins tGPR:$Rt, AddrMode_r:$addr),
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am, itin_r, asm, "\t$Rt, $addr",
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[(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
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def i :
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def i : // reg/imm5
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T1pILdStEncodeImm<imm_opc, 0 /* Store */,
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(outs), (ins tGPR:$Rt, AddrMode_i:$addr),
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am, itin_i, asm, "\t$Rt, $addr",
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