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Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21412 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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63b3afa984
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34695381d6
@ -1,10 +1,10 @@
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//===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
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//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes an abstract interface used to get information about a
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@ -92,7 +92,7 @@ public:
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virtual iterator allocation_order_end(MachineFunction &MF) const {
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return end();
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}
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/// getSize - Return the size of the register in bytes, which is also the size
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@ -280,7 +280,7 @@ public:
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/// instructions. This method need only be implemented if using call frame
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/// setup/destroy pseudo instructions.
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///
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virtual void
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virtual void
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eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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@ -1,14 +1,14 @@
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//===-- llvm/Target/TargetData.h - Data size & alignment info ---*- C++ -*-===//
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//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines target properties related to datatype size/offset/alignment
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// information. It uses lazy annotations to cache information about how
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// information. It uses lazy annotations to cache information about how
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// structure types are laid out and used.
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//
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// This structure should be created once, filled in if the defaults are not
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@ -49,7 +49,7 @@ public:
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bool LittleEndian = false,
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unsigned char PtrSize = 8,
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unsigned char PtrAl = 8, unsigned char DoubleAl = 8,
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unsigned char FloatAl = 4, unsigned char LongAl = 8,
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unsigned char FloatAl = 4, unsigned char LongAl = 8,
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unsigned char IntAl = 4, unsigned char ShortAl = 2,
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unsigned char ByteAl = 1, unsigned char BoolAl = 1);
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@ -67,7 +67,7 @@ public:
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PointerSize(TD.getPointerSize()),
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PointerAlignment(TD.getPointerAlignment()) {
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}
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TargetData(const std::string &ToolName, const Module *M);
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~TargetData(); // Not virtual, do not subclass this class
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@ -105,9 +105,9 @@ public:
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/// getIndexOffset - return the offset from the beginning of the type for the
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/// specified indices. This is used to implement getelementptr.
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///
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uint64_t getIndexedOffset(const Type *Ty,
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uint64_t getIndexedOffset(const Type *Ty,
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const std::vector<Value*> &Indices) const;
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const StructLayout *getStructLayout(const StructType *Ty) const;
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};
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//===-- llvm/Target/TargetFrameInfo.h ---------------------------*- C++ -*-===//
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//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//
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//===----------------------------------------------------------------------===//
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//
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// Interface to describe the layout of a stack frame on the target machine.
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@ -67,13 +67,13 @@ public:
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/// fixed offset from the incoming stack pointer that each register should be
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/// spilled at. If a register is not listed here, the code generator is
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/// allowed to spill it anywhere it chooses.
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///
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///
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virtual const std::pair<unsigned, int> *
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getCalleeSaveSpillSlots(unsigned &NumEntries) const {
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NumEntries = 0;
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return 0;
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}
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//===--------------------------------------------------------------------===//
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// These methods provide details of the stack frame used by Sparc, thus they
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// are Sparc specific.
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@ -87,12 +87,12 @@ public:
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// function. The frame contents are obtained from the MachineFunction object
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// for the given function. The rest must be implemented by the
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// machine-specific subclass.
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//
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//
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virtual int getIncomingArgOffset (MachineFunction& mcInfo,
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unsigned argNum) const;
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virtual int getOutgoingArgOffset (MachineFunction& mcInfo,
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unsigned argNum) const;
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virtual int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
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bool& growUp) const;
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virtual int getRegSpillAreaOffset (MachineFunction& mcInfo,
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//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
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//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the target machine instructions to the code generator.
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@ -91,14 +91,14 @@ public:
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//---------------------------------------------------------------------------
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///
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///
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/// TargetInstrInfo - Interface to description of machine instructions
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///
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///
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class TargetInstrInfo {
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const TargetInstrDescriptor* desc; // raw array to allow static init'n
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unsigned NumOpcodes; // number of entries in the desc array
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unsigned numRealOpCodes; // number of non-dummy op codes
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TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
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public:
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@ -107,9 +107,9 @@ public:
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// Invariant: All instruction sets use opcode #0 as the PHI instruction
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enum { PHI = 0 };
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unsigned getNumOpcodes() const { return NumOpcodes; }
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/// get - Return the machine instruction descriptor that corresponds to the
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/// specified instruction opcode.
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///
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const char *getName(MachineOpCode Opcode) const {
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return get(Opcode).Name;
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}
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int getNumOperands(MachineOpCode Opcode) const {
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return get(Opcode).numOperands;
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}
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@ -143,7 +143,7 @@ public:
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//
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// Query instruction class flags according to the machine-independent
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// flags listed above.
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//
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//
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bool isReturn(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_RET_FLAG;
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}
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@ -253,36 +253,36 @@ public:
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return true;
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}
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//
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//
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// Latencies for individual instructions and instruction pairs
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//
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//
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virtual int minLatency(MachineOpCode Opcode) const {
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return get(Opcode).latency;
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}
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virtual int maxLatency(MachineOpCode Opcode) const {
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return get(Opcode).latency;
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}
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//
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// Which operand holds an immediate constant? Returns -1 if none
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//
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//
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virtual int getImmedConstantPos(MachineOpCode Opcode) const {
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return -1; // immediate position is machine specific, so say -1 == "none"
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}
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// Check if the specified constant fits in the immediate field
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// of this machine instruction
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//
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//
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virtual bool constantFitsInImmedField(MachineOpCode Opcode,
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int64_t intValue) const;
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// Return the largest positive constant that can be held in the IMMED field
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// of this machine instruction.
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// isSignExtended is set to true if the value is sign-extended before use
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// (this is true for all immediate fields in SPARC instructions).
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// Return 0 if the instruction has no IMMED field.
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//
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//
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virtual uint64_t maxImmedConstant(MachineOpCode Opcode,
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bool &isSignExtended) const {
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isSignExtended = get(Opcode).immedIsSignExtended;
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//===- Target/TargetJITInfo.h - Target Information for JIT ------*- C++ -*-===//
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//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//
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//===----------------------------------------------------------------------===//
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//
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// This file exposes an abstract interface used by the Just-In-Time code
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@ -30,19 +30,19 @@ namespace llvm {
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class TargetJITInfo {
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public:
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virtual ~TargetJITInfo() {}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast code generator for this target.
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///
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virtual void addPassesToJITCompile(FunctionPassManager &PM) = 0;
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/// replaceMachineCodeForFunction - Make it so that calling the function
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/// whose machine code is at OLD turns into a call to NEW, perhaps by
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/// overwriting OLD with a branch to NEW. This is used for self-modifying
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/// code.
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///
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virtual void replaceMachineCodeForFunction(void *Old, void *New) = 0;
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/// emitFunctionStub - Use the specified MachineCodeEmitter object to emit a
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/// small native function that simply calls the function at the specified
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/// address. Return the address of the resultant function.
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//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
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//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes how to lower LLVM code to machine code. This has two
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TargetMachine &getTargetMachine() const { return TM; }
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const TargetData &getTargetData() const { return TD; }
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bool isLittleEndian() const { return IsLittleEndian; }
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MVT::ValueType getPointerTy() const { return PointerTy; }
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MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
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@ -92,7 +92,7 @@ public:
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assert(RC && "This value type is not natively supported!");
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return RC;
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}
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/// hasNativeSupportFor - Return true if the target has native support for the
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/// specified value type. This means that it has a register that directly
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/// holds it without promotions or expansions.
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@ -117,7 +117,7 @@ public:
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MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
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return TransformToType[VT];
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}
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typedef std::vector<double>::const_iterator legal_fpimm_iterator;
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legal_fpimm_iterator legal_fpimm_begin() const {
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return LegalFPImmediates.begin();
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return LegalFPImmediates.end();
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}
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/// getOperationAction - Return how this operation should be
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/// getOperationAction - Return how this operation should be
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LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
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return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
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return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
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}
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/// hasNativeSupportForOperation - Return true if this operation is legal for
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/// this type.
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///
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@ -173,7 +173,7 @@ public:
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case Type::PointerTyID: return PointerTy;
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}
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}
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/// getNumElements - Return the number of registers that this ValueType will
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/// eventually require. This is always one for all non-integer types, is
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/// one for any types promoted to live in larger registers, but may be more
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@ -206,7 +206,7 @@ protected:
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void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
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ShiftAmtHandling = OORSA;
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}
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/// addRegisterClass - Add the specified register class as an available
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/// regclass for the specified value type. This indicates the selector can
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/// handle values of that class natively.
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@ -218,7 +218,7 @@ protected:
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/// computeRegisterProperties - Once all of the register classes are added,
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/// this allows us to compute derived properties we expose.
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void computeRegisterProperties();
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/// setOperationAction - Indicate that the specified operation does not work
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/// with the specified type and indicate what to do about it.
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void setOperationAction(unsigned Op, MVT::ValueType VT,
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@ -291,7 +291,7 @@ public:
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/// implement this. The default implementation of this aborts.
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virtual SDOperand LowerOperation(SDOperand Op);
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private:
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TargetMachine &TM;
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const TargetData &TD;
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@ -299,7 +299,7 @@ private:
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/// IsLittleEndian - True if this is a little endian target.
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///
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bool IsLittleEndian;
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/// PointerTy - The type to use for pointers, usually i32 or i64.
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///
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MVT::ValueType PointerTy;
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@ -327,7 +327,7 @@ private:
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/// value type, where the two bits correspond to the LegalizeAction enum.
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/// This can be queried with "getTypeAction(VT)".
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unsigned ValueTypeActions;
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/// TransformToType - For any value types we are promoting or expanding, this
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/// contains the value type that we are changing to. For Expanded types, this
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/// contains one step of the expand (e.g. i64 -> i32), even if there are
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@ -341,9 +341,9 @@ private:
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/// operations that are not should be described. Note that operations on
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/// non-legal value types are not described here.
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unsigned OpActions[128];
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std::vector<double> LegalFPImmediates;
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|
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std::vector<std::pair<MVT::ValueType,
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TargetRegisterClass*> > AvailableRegClasses;
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};
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|
@ -1,10 +1,10 @@
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//===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
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// This file describes the general parts of a Target machine.
|
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@ -37,16 +37,16 @@ class IntrinsicLowering;
|
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/// TargetMachine - Primary interface to the complete machine description for
|
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/// the target machine. All target-specific information should be accessible
|
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/// through this interface.
|
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///
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///
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class TargetMachine {
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const std::string Name;
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const TargetData DataLayout; // Calculates type size & alignment
|
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IntrinsicLowering *IL; // Specifies how to lower intrinsic calls
|
||||
|
||||
|
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TargetMachine(const TargetMachine&); // DO NOT IMPLEMENT
|
||||
void operator=(const TargetMachine&); // DO NOT IMPLEMENT
|
||||
protected: // Can only create subclasses...
|
||||
TargetMachine(const std::string &name, IntrinsicLowering *IL,
|
||||
TargetMachine(const std::string &name, IntrinsicLowering *IL,
|
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bool LittleEndian = false,
|
||||
unsigned char PtrSize = 8, unsigned char PtrAl = 8,
|
||||
unsigned char DoubleAl = 8, unsigned char FloatAl = 4,
|
||||
@ -54,7 +54,7 @@ protected: // Can only create subclasses...
|
||||
unsigned char ShortAl = 2, unsigned char ByteAl = 1,
|
||||
unsigned char BoolAl = 1);
|
||||
|
||||
TargetMachine(const std::string &name, IntrinsicLowering *IL,
|
||||
TargetMachine(const std::string &name, IntrinsicLowering *IL,
|
||||
const TargetData &TD);
|
||||
|
||||
/// This constructor is used for targets that support arbitrary TargetData
|
||||
@ -87,12 +87,12 @@ public:
|
||||
/// lower unknown intrinsic functions to the equivalent LLVM expansion.
|
||||
///
|
||||
IntrinsicLowering &getIntrinsicLowering() const { return *IL; }
|
||||
|
||||
|
||||
// Interfaces to the major aspects of target machine information:
|
||||
// -- Instruction opcode and operand information
|
||||
// -- Pipelines and scheduling information
|
||||
// -- Stack frame information
|
||||
//
|
||||
//
|
||||
virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
|
||||
virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
|
||||
const TargetData &getTargetData() const { return DataLayout; }
|
||||
|
@ -1,10 +1,10 @@
|
||||
//===-- Target/TargetMachineRegistry.h - Target Registration ----*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file exposes two classes: the TargetMachineRegistry class, which allows
|
||||
@ -74,7 +74,7 @@ namespace llvm {
|
||||
/// TargetMachine comments..
|
||||
template<class TargetMachineImpl>
|
||||
struct RegisterTarget : public TargetMachineRegistry::Entry {
|
||||
RegisterTarget(const char *Name, const char *ShortDesc) :
|
||||
RegisterTarget(const char *Name, const char *ShortDesc) :
|
||||
TargetMachineRegistry::Entry(Name, ShortDesc, &Allocator,
|
||||
&TargetMachineImpl::getModuleMatchQuality,
|
||||
&TargetMachineImpl::getJITMatchQuality) {
|
||||
@ -94,7 +94,7 @@ namespace llvm {
|
||||
virtual ~TargetRegistrationListener();
|
||||
|
||||
TargetRegistrationListener *getNext() const { return Next; }
|
||||
|
||||
|
||||
virtual void targetRegistered(const TargetMachineRegistry::Entry *E) = 0;
|
||||
};
|
||||
|
||||
|
@ -1,10 +1,10 @@
|
||||
//===-- llvm/Target/TargetOptions.h - Target Options ------------*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file defines command line option flags that are shared across various
|
||||
|
@ -1,10 +1,10 @@
|
||||
//===- Target/TargetSchedInfo.h - Target Instruction Sched Info -*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file describes the target machine to the instruction scheduler.
|
||||
@ -22,14 +22,14 @@
|
||||
|
||||
namespace llvm {
|
||||
|
||||
typedef long long CycleCount_t;
|
||||
typedef long long CycleCount_t;
|
||||
static const CycleCount_t HUGE_LATENCY = ~((long long) 1 << (sizeof(CycleCount_t)-2));
|
||||
static const CycleCount_t INVALID_LATENCY = -HUGE_LATENCY;
|
||||
static const CycleCount_t INVALID_LATENCY = -HUGE_LATENCY;
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// class MachineResource
|
||||
// class MachineResource
|
||||
// class CPUResource
|
||||
//
|
||||
//
|
||||
// Purpose:
|
||||
// Representation of a single machine resource used in specifying
|
||||
// resource usages of machine instructions for scheduling.
|
||||
@ -42,7 +42,7 @@ struct CPUResource {
|
||||
const std::string rname;
|
||||
resourceId_t rid;
|
||||
int maxNumUsers; // MAXINT if no restriction
|
||||
|
||||
|
||||
CPUResource(const std::string& resourceName, int maxUsers);
|
||||
static CPUResource* getCPUResource(resourceId_t id);
|
||||
private:
|
||||
@ -52,17 +52,17 @@ private:
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// struct InstrClassRUsage
|
||||
// struct InstrRUsageDelta
|
||||
// struct InstrIssueDelta
|
||||
// struct InstrRUsage
|
||||
//
|
||||
// struct InstrRUsageDelta
|
||||
// struct InstrIssueDelta
|
||||
// struct InstrRUsage
|
||||
//
|
||||
// Purpose:
|
||||
// The first three are structures used to specify machine resource
|
||||
// The first three are structures used to specify machine resource
|
||||
// usages for each instruction in a machine description file:
|
||||
// InstrClassRUsage : resource usages common to all instrs. in a class
|
||||
// InstrRUsageDelta : add/delete resource usage for individual instrs.
|
||||
// InstrIssueDelta : add/delete instr. issue info for individual instrs
|
||||
//
|
||||
// InstrRUsageDelta : add/delete resource usage for individual instrs.
|
||||
// InstrIssueDelta : add/delete instr. issue info for individual instrs
|
||||
//
|
||||
// The last one (InstrRUsage) is the internal representation of
|
||||
// instruction resource usage constructed from the above three.
|
||||
//---------------------------------------------------------------------------
|
||||
@ -73,18 +73,18 @@ const int MAX_NUM_CYCLES = 32;
|
||||
struct InstrClassRUsage {
|
||||
InstrSchedClass schedClass;
|
||||
int totCycles;
|
||||
|
||||
|
||||
// Issue restrictions common to instructions in this class
|
||||
unsigned maxNumIssue;
|
||||
bool isSingleIssue;
|
||||
bool breaksGroup;
|
||||
CycleCount_t numBubbles;
|
||||
|
||||
|
||||
// Feasible slots to use for instructions in this class.
|
||||
// The size of vector S[] is `numSlots'.
|
||||
unsigned numSlots;
|
||||
unsigned feasibleSlots[MAX_NUM_SLOTS];
|
||||
|
||||
|
||||
// Resource usages common to instructions in this class.
|
||||
// The size of vector V[] is `numRUEntries'.
|
||||
unsigned numRUEntries;
|
||||
@ -104,7 +104,7 @@ struct InstrRUsageDelta {
|
||||
|
||||
// Specify instruction issue restrictions for individual instructions
|
||||
// that differ from the common rules for the class.
|
||||
//
|
||||
//
|
||||
struct InstrIssueDelta {
|
||||
MachineOpCode opCode;
|
||||
bool isSingleIssue;
|
||||
@ -115,19 +115,19 @@ struct InstrIssueDelta {
|
||||
|
||||
struct InstrRUsage {
|
||||
bool sameAsClass;
|
||||
|
||||
|
||||
// Issue restrictions for this instruction
|
||||
bool isSingleIssue;
|
||||
bool breaksGroup;
|
||||
CycleCount_t numBubbles;
|
||||
|
||||
|
||||
// Feasible slots to use for this instruction.
|
||||
std::vector<bool> feasibleSlots;
|
||||
|
||||
|
||||
// Resource usages for this instruction, with one resource vector per cycle.
|
||||
CycleCount_t numCycles;
|
||||
std::vector<std::vector<resourceId_t> > resourcesByCycle;
|
||||
|
||||
|
||||
private:
|
||||
// Conveniences for initializing this structure
|
||||
void setTo(const InstrClassRUsage& classRU);
|
||||
@ -143,22 +143,22 @@ private:
|
||||
void setMaxSlots (int maxNumSlots) {
|
||||
feasibleSlots.resize(maxNumSlots);
|
||||
}
|
||||
|
||||
|
||||
friend class TargetSchedInfo; // give access to these functions
|
||||
};
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
/// TargetSchedInfo - Common interface to machine information for
|
||||
/// TargetSchedInfo - Common interface to machine information for
|
||||
/// instruction scheduling
|
||||
///
|
||||
class TargetSchedInfo {
|
||||
public:
|
||||
const TargetMachine& target;
|
||||
|
||||
|
||||
unsigned maxNumIssueTotal;
|
||||
int longestIssueConflict;
|
||||
|
||||
|
||||
protected:
|
||||
inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
|
||||
assert(opCode >= 0 && opCode < (int) instrRUsages.size());
|
||||
@ -181,19 +181,19 @@ public:
|
||||
unsigned _numUsageDeltas,
|
||||
unsigned _numIssueDeltas);
|
||||
/*dtor*/ virtual ~TargetSchedInfo() {}
|
||||
|
||||
|
||||
inline const TargetInstrInfo& getInstrInfo() const {
|
||||
return *mii;
|
||||
}
|
||||
|
||||
|
||||
inline int getNumSchedClasses() const {
|
||||
return numSchedClasses;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
inline unsigned getMaxNumIssueTotal() const {
|
||||
return maxNumIssueTotal;
|
||||
}
|
||||
|
||||
|
||||
inline unsigned getMaxIssueForClass(const InstrSchedClass& sc) const {
|
||||
assert(sc < numSchedClasses);
|
||||
return classRUsages[sc].maxNumIssue;
|
||||
@ -201,14 +201,14 @@ public:
|
||||
|
||||
inline InstrSchedClass getSchedClass (MachineOpCode opCode) const {
|
||||
return getInstrInfo().getSchedClass(opCode);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
inline bool instrCanUseSlot (MachineOpCode opCode,
|
||||
unsigned s) const {
|
||||
assert(s < getInstrRUsage(opCode).feasibleSlots.size() && "Invalid slot!");
|
||||
return getInstrRUsage(opCode).feasibleSlots[s];
|
||||
}
|
||||
|
||||
|
||||
inline int getLongestIssueConflict () const {
|
||||
return longestIssueConflict;
|
||||
}
|
||||
@ -229,15 +229,15 @@ public:
|
||||
inline bool isSingleIssue (MachineOpCode opCode) const {
|
||||
return getInstrRUsage(opCode).isSingleIssue;
|
||||
}
|
||||
|
||||
|
||||
inline bool breaksIssueGroup (MachineOpCode opCode) const {
|
||||
return getInstrRUsage(opCode).breaksGroup;
|
||||
}
|
||||
|
||||
|
||||
inline unsigned numBubblesAfter (MachineOpCode opCode) const {
|
||||
return getInstrRUsage(opCode).numBubbles;
|
||||
}
|
||||
|
||||
|
||||
inline unsigned getCPUResourceNum(int rd)const{
|
||||
for(unsigned i=0;i<resourceNumVector.size();i++){
|
||||
if(resourceNumVector[i].first == rd) return resourceNumVector[i].second;
|
||||
@ -245,25 +245,25 @@ public:
|
||||
assert( 0&&"resource not found");
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
protected:
|
||||
virtual void initializeResources ();
|
||||
|
||||
|
||||
private:
|
||||
void computeInstrResources(const std::vector<InstrRUsage>& instrRUForClasses);
|
||||
void computeIssueGaps(const std::vector<InstrRUsage>& instrRUForClasses);
|
||||
|
||||
|
||||
void setGap(int gap, MachineOpCode fromOp, MachineOpCode toOp) {
|
||||
std::vector<int>& toGaps = issueGaps[fromOp];
|
||||
if (toOp >= (int) toGaps.size())
|
||||
toGaps.resize(toOp+1);
|
||||
toGaps[toOp] = gap;
|
||||
}
|
||||
|
||||
|
||||
public:
|
||||
std::vector<std::pair<int,int> > resourceNumVector;
|
||||
|
||||
|
||||
protected:
|
||||
unsigned numSchedClasses;
|
||||
const TargetInstrInfo* mii;
|
||||
@ -272,7 +272,7 @@ protected:
|
||||
const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
|
||||
unsigned numUsageDeltas;
|
||||
unsigned numIssueDeltas;
|
||||
|
||||
|
||||
std::vector<InstrRUsage> instrRUsages; // indexed by opcode
|
||||
std::vector<std::vector<int> > issueGaps; // indexed by [opcode1][opcode2]
|
||||
std::vector<std::vector<MachineOpCode> >
|
||||
@ -281,7 +281,7 @@ protected:
|
||||
|
||||
friend class ModuloSchedulingPass;
|
||||
friend class MSSchedule;
|
||||
|
||||
|
||||
};
|
||||
|
||||
} // End llvm namespace
|
||||
|
@ -1,10 +1,10 @@
|
||||
//===- llvm/Transforms/IPO.h - Interprocedural Transformations --*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This header file defines prototypes for accessor functions that expose passes
|
||||
@ -77,7 +77,7 @@ ModulePass *createGlobalDCEPass();
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
/// createFunctionExtractionPass - If deleteFn is true, this pass deletes as
|
||||
/// createFunctionExtractionPass - If deleteFn is true, this pass deletes as
|
||||
/// the specified function. Otherwise, it deletes as much of the module as
|
||||
/// possible, except for the function specified.
|
||||
///
|
||||
|
@ -1,10 +1,10 @@
|
||||
//===- Transforms/Instrumentation.h - Instrumentation passes ----*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This files defines constructor functions for instrumentation passes.
|
||||
|
@ -1,10 +1,10 @@
|
||||
//===- llvm/Transforms/LinkAllPasses.h - Reference All Passes ---*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by Jeff Cohen and is distributed under the
|
||||
// University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This header file is required for building with Microsoft's VC++, as it has
|
||||
|
@ -1,10 +1,10 @@
|
||||
//===-- Scalar.h - Scalar Transformations -----------------------*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This header file defines prototypes for accessor functions that expose passes
|
||||
@ -231,7 +231,7 @@ FunctionPass *createLoopSimplifyPass();
|
||||
extern const PassInfo *LoopSimplifyID;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
// This pass eliminates call instructions to the current function which occur
|
||||
// immediately before return instructions.
|
||||
//
|
||||
@ -274,7 +274,7 @@ FunctionPass *createLowerPackedPass();
|
||||
FunctionPass *createLowerInvokePass();
|
||||
extern const PassInfo *LowerInvokePassID;
|
||||
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
/// createLowerGCPass - This function returns an instance of the "lowergc"
|
||||
/// pass, which lowers garbage collection intrinsics to normal LLVM code.
|
||||
|
@ -1,10 +1,10 @@
|
||||
//===-- Transform/Utils/BasicBlockUtils.h - BasicBlock Utils ----*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This family of functions perform manipulations on basic blocks, and
|
||||
|
@ -1,10 +1,10 @@
|
||||
//===- Cloning.h - Clone various parts of LLVM programs ---------*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file defines various functions that are used to clone chunks of LLVM
|
||||
@ -108,7 +108,7 @@ void CloneTraceInto(Function *NewFunc, Trace &T,
|
||||
/// this call. The program is still in a well defined state if this occurs
|
||||
/// though.
|
||||
///
|
||||
/// Note that this only does one level of inlining. For example, if the
|
||||
/// Note that this only does one level of inlining. For example, if the
|
||||
/// instruction 'call B' is inlined, and 'B' calls 'C', then the call to 'C' now
|
||||
/// exists in the instruction stream. Similiarly this will inline a recursive
|
||||
/// function by one level.
|
||||
@ -117,9 +117,9 @@ bool InlineFunction(CallInst *C);
|
||||
bool InlineFunction(InvokeInst *II);
|
||||
bool InlineFunction(CallSite CS);
|
||||
|
||||
/// CloneTrace - Returns a copy of the specified trace.
|
||||
/// It takes a vector of basic blocks clones the basic blocks, removes internal
|
||||
/// phi nodes, adds it to the same function as the original (although there is
|
||||
/// CloneTrace - Returns a copy of the specified trace.
|
||||
/// It takes a vector of basic blocks clones the basic blocks, removes internal
|
||||
/// phi nodes, adds it to the same function as the original (although there is
|
||||
/// no jump to it) and returns the new vector of basic blocks.
|
||||
std::vector<BasicBlock *> CloneTrace(const std::vector<BasicBlock*> &origTrace);
|
||||
|
||||
|
@ -1,10 +1,10 @@
|
||||
//===-- Transform/Utils/FunctionUtils.h - Function Utils --------*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This family of transformations manipulate LLVM functions.
|
||||
@ -21,7 +21,7 @@ namespace llvm {
|
||||
struct DominatorSet;
|
||||
class Function;
|
||||
class Loop;
|
||||
|
||||
|
||||
/// ExtractCodeRegion - rip out a sequence of basic blocks into a new function
|
||||
///
|
||||
Function* ExtractCodeRegion(DominatorSet &DS,
|
||||
|
@ -1,10 +1,10 @@
|
||||
//===-- Local.h - Functions to perform local transformations ----*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This family of functions perform various local transformations to the
|
||||
|
@ -1,10 +1,10 @@
|
||||
//===- PromoteMemToReg.h - Promote Allocas to Scalars -----------*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file exposes an interface to promote alloca instructions to SSA
|
||||
|
@ -1,10 +1,10 @@
|
||||
//===-- UnifyFunctionExitNodes.h - Ensure fn's have one return --*- C++ -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This pass is used to ensure that functions have at most one return and one
|
||||
|
Loading…
Reference in New Issue
Block a user