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- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.

Browse Source 
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-07-20 07:51:56 +00:00
parent 4c8164813c
commit 34ad6db8b9
54 changed files with 277 additions and 232 deletions
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6
include/llvm/ExecutionEngine/ExecutionEngine.h
View File

@ -480,7 +480,7 @@ private:
JMM = NULL;
AllocateGVsWithCode = false;
RelocModel = Reloc::Default;
CMModel = CodeModel::Default;
CMModel = CodeModel::JITDefault;
UseMCJIT = false;
}
@ -529,7 +529,8 @@ public:
}
/// setCodeModel - Set the CodeModel that the ExecutionEngine target
/// data is using. Defaults to target specific default "CodeModel::Default".
/// data is using. Defaults to target specific default
/// "CodeModel::JITDefault".
EngineBuilder &setCodeModel(CodeModel::Model M) {
CMModel = M;
return *this;
@ -581,6 +582,7 @@ public:
StringRef MCPU,
const SmallVectorImpl<std::string>& MAttrs,
Reloc::Model RM,
CodeModel::Model CM,
std::string *Err);
ExecutionEngine *create();

15
include/llvm/MC/MCCodeGenInfo.h
View File

@ -16,20 +16,33 @@
#define LLVM_MC_MCCODEGENINFO_H
namespace llvm {
// Relocation model types.
namespace Reloc {
enum Model { Default, Static, PIC_, DynamicNoPIC };
}
// Code model types.
namespace CodeModel {
enum Model { Default, JITDefault, Small, Kernel, Medium, Large };
}
class MCCodeGenInfo {
/// RelocationModel - Relocation model: statcic, pic, etc.
///
Reloc::Model RelocationModel;
/// CMModel - Code model.
///
CodeModel::Model CMModel;
public:
void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default);
void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default,
CodeModel::Model CM = CodeModel::Default);
Reloc::Model getRelocationModel() const { return RelocationModel; }
CodeModel::Model getCodeModel() const { return CMModel; }
};
} // namespace llvm

24
include/llvm/Target/TargetMachine.h
View File

@ -43,17 +43,6 @@ class TargetSubtargetInfo;
class formatted_raw_ostream;
class raw_ostream;
// Code model types.
namespace CodeModel {
enum Model {
Default,
Small,
Kernel,
Medium,
Large
};
}
// Code generation optimization level.
namespace CodeGenOpt {
enum Level {
@ -101,7 +90,6 @@ protected: // Can only create subclasses.
std::string TargetFS;
/// CodeGenInfo - Low level target information such as relocation model.
///
const MCCodeGenInfo *CodeGenInfo;
/// AsmInfo - Contains target specific asm information.
@ -214,11 +202,7 @@ public:
/// getCodeModel - Returns the code model. The choices are small, kernel,
/// medium, large, and target default.
static CodeModel::Model getCodeModel();
/// setCodeModel - Sets the code model.
///
static void setCodeModel(CodeModel::Model Model);
CodeModel::Model getCodeModel() const;
/// getAsmVerbosityDefault - Returns the default value of asm verbosity.
///
@ -301,7 +285,8 @@ public:
class LLVMTargetMachine : public TargetMachine {
protected: // Can only create subclasses.
LLVMTargetMachine(const Target &T, StringRef TargetTriple,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
private:
/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
@ -310,9 +295,6 @@ private:
bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
bool DisableVerify, MCContext *&OutCtx);
virtual void setCodeModelForJIT();
virtual void setCodeModelForStatic();
public:
/// addPassesToEmitFile - Add passes to the specified pass manager to get the
/// specified file emitted. Typically this will involve several steps of code

27
include/llvm/Target/TargetRegistry.h
View File

@ -70,7 +70,9 @@ namespace llvm {
typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T,
StringRef TT);
typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT, Reloc::Model M);
typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT,
Reloc::Model RM,
CodeModel::Model CM);
typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
@ -80,7 +82,8 @@ namespace llvm {
StringRef TT,
StringRef CPU,
StringRef Features,
Reloc::Model RM);
Reloc::Model RM,
CodeModel::Model CM);
typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM,
MCStreamer &Streamer);
typedef TargetAsmBackend *(*AsmBackendCtorTy)(const Target &T,
@ -263,10 +266,11 @@ namespace llvm {
/// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
///
MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model M) const {
MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM,
CodeModel::Model CM) const {
if (!MCCodeGenInfoCtorFn)
return 0;
return MCCodeGenInfoCtorFn(Triple, M);
return MCCodeGenInfoCtorFn(Triple, RM, CM);
}
/// createMCInstrInfo - Create a MCInstrInfo implementation.
@ -309,11 +313,12 @@ namespace llvm {
/// either the target triple from the module, or the target triple of the
/// host if that does not exist.
TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU,
StringRef Features,
Reloc::Model RM = Reloc::Default) const {
StringRef Features,
Reloc::Model RM = Reloc::Default,
CodeModel::Model CM = CodeModel::Default) const {
if (!TargetMachineCtorFn)
return 0;
return TargetMachineCtorFn(*this, Triple, CPU, Features, RM);
return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM);
}
/// createAsmBackend - Create a target specific assembly parser.
@ -802,7 +807,8 @@ namespace llvm {
TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator);
}
private:
static MCCodeGenInfo *Allocator(StringRef TT, Reloc::Model M) {
static MCCodeGenInfo *Allocator(StringRef TT,
Reloc::Model RM, CodeModel::Model CM) {
return new MCCodeGenInfoImpl();
}
};
@ -938,8 +944,9 @@ namespace llvm {
private:
static TargetMachine *Allocator(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM) {
return new TargetMachineImpl(T, TT, CPU, FS, RM);
Reloc::Model RM,
CodeModel::Model CM) {
return new TargetMachineImpl(T, TT, CPU, FS, RM, CM);
}
};

23
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -105,23 +105,12 @@ EnableFastISelOption("fast-isel", cl::Hidden,
LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
StringRef CPU, StringRef FS,
Reloc::Model RM)
Reloc::Model RM, CodeModel::Model CM)
: TargetMachine(T, Triple, CPU, FS) {
CodeGenInfo = T.createMCCodeGenInfo(Triple, RM);
CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM);
AsmInfo = T.createMCAsmInfo(Triple);
}
// Set the default code model for the JIT for a generic target.
// FIXME: Is small right here? or .is64Bit() ? Large : Small?
void LLVMTargetMachine::setCodeModelForJIT() {
setCodeModel(CodeModel::Small);
}
// Set the default code model for static compilation for a generic target.
void LLVMTargetMachine::setCodeModelForStatic() {
setCodeModel(CodeModel::Small);
}
bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out,
CodeGenFileType FileType,
@ -201,8 +190,6 @@ bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
PM.add(Printer);
// Make sure the code model is set.
setCodeModelForStatic();
PM.add(createGCInfoDeleter());
return false;
}
@ -217,9 +204,6 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
JITCodeEmitter &JCE,
CodeGenOpt::Level OptLevel,
bool DisableVerify) {
// Make sure the code model is set.
setCodeModelForJIT();
// Add common CodeGen passes.
MCContext *Ctx = 0;
if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
@ -273,9 +257,6 @@ bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
PM.add(Printer);
// Make sure the code model is set.
setCodeModelForJIT();
return false; // success!
}

8
lib/ExecutionEngine/ExecutionEngine.cpp
View File

@ -437,9 +437,8 @@ ExecutionEngine *ExecutionEngine::createJIT(Module *M,
SmallVector<std::string, 1> MAttrs;
TargetMachine *TM =
EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, RM, ErrorStr);
EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, RM, CMM, ErrorStr);
if (!TM || (ErrorStr && ErrorStr->length() > 0)) return 0;
TM->setCodeModel(CMM);
return ExecutionEngine::JITCtor(M, ErrorStr, JMM, OptLevel, GVsWithCode, TM);
}
@ -467,9 +466,8 @@ ExecutionEngine *EngineBuilder::create() {
// try making a JIT.
if (WhichEngine & EngineKind::JIT) {
if (TargetMachine *TM = EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs,
RelocModel, ErrorStr)) {
TM->setCodeModel(CMModel);
RelocModel, CMModel,
ErrorStr)) {
if (UseMCJIT && ExecutionEngine::MCJITCtor) {
ExecutionEngine *EE =
ExecutionEngine::MCJITCtor(M, ErrorStr, JMM, OptLevel,

2
lib/ExecutionEngine/JIT/JIT.h
View File

@ -101,7 +101,7 @@ public:
CodeGenOpt::Default,
bool GVsWithCode = true,
Reloc::Model RM = Reloc::Default,
CodeModel::Model CMM = CodeModel::Default) {
CodeModel::Model CMM = CodeModel::JITDefault) {
return ExecutionEngine::createJIT(M, Err, JMM, OptLevel, GVsWithCode,
RM, CMM);
}

4
lib/ExecutionEngine/TargetSelect.cpp
View File

@ -31,6 +31,7 @@ TargetMachine *EngineBuilder::selectTarget(Module *Mod,
StringRef MCPU,
const SmallVectorImpl<std::string>& MAttrs,
Reloc::Model RM,
CodeModel::Model CM,
std::string *ErrorStr) {
Triple TheTriple(Mod->getTargetTriple());
if (TheTriple.getTriple().empty())
@ -85,7 +86,8 @@ TargetMachine *EngineBuilder::selectTarget(Module *Mod,
// Allocate a target...
TargetMachine *Target = TheTarget->createTargetMachine(TheTriple.getTriple(),
MCPU, FeaturesStr, RM);
MCPU, FeaturesStr,
RM, CM);
assert(Target && "Could not allocate target machine!");
return Target;
}

3
lib/MC/MCCodeGenInfo.cpp
View File

@ -15,6 +15,7 @@
#include "llvm/MC/MCCodeGenInfo.h"
using namespace llvm;
void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM) {
void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM) {
RelocationModel = RM;
CMModel = CM;
}

12
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -64,8 +64,8 @@ extern "C" void LLVMInitializeARMTarget() {
///
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
Reloc::Model RM, CodeModel::Model CM)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
Subtarget(TT, CPU, FS),
JITInfo(),
InstrItins(Subtarget.getInstrItineraryData()) {
@ -76,8 +76,8 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: ARMBaseTargetMachine(T, TT, CPU, FS, RM), InstrInfo(Subtarget),
Reloc::Model RM, CodeModel::Model CM)
: ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget),
DataLayout(Subtarget.isAPCS_ABI() ?
std::string("e-p:32:32-f64:32:64-i64:32:64-"
"v128:32:128-v64:32:64-n32") :
@ -94,8 +94,8 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: ARMBaseTargetMachine(T, TT, CPU, FS, RM),
Reloc::Model RM, CodeModel::Model CM)
: ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM),
InstrInfo(Subtarget.hasThumb2()
? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
: ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),

9
lib/Target/ARM/ARMTargetMachine.h
View File

@ -40,7 +40,8 @@ private:
public:
ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
@ -69,7 +70,8 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
ARMFrameLowering FrameLowering;
public:
ARMTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
virtual const ARMRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
@ -108,7 +110,8 @@ class ThumbTargetMachine : public ARMBaseTargetMachine {
OwningPtr<ARMFrameLowering> FrameLowering;
public:
ThumbTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
/// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
virtual const ARMBaseRegisterInfo *getRegisterInfo() const {

5
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@ -143,11 +143,12 @@ extern "C" void LLVMInitializeARMMCAsmInfo() {
RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
}
MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default)
RM = Reloc::DynamicNoPIC;
X->InitMCCodeGenInfo(RM);
X->InitMCCodeGenInfo(RM, CM);
return X;
}

6
lib/Target/Alpha/AlphaTargetMachine.cpp
View File

@ -23,9 +23,9 @@ extern "C" void LLVMInitializeAlphaTarget() {
}
AlphaTargetMachine::AlphaTargetMachine(const Target &T, StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
DataLayout("e-f128:128:128-n64"),
FrameLowering(Subtarget),
Subtarget(TT, CPU, FS),

3
lib/Target/Alpha/AlphaTargetMachine.h
View File

@ -37,7 +37,8 @@ class AlphaTargetMachine : public LLVMTargetMachine {
public:
AlphaTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {

5
lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp
View File

@ -66,9 +66,10 @@ extern "C" void LLVMInitializeAlphaMCAsmInfo() {
RegisterMCAsmInfo<AlphaMCAsmInfo> X(TheAlphaTarget);
}
MCCodeGenInfo *createAlphaMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *createAlphaMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(Reloc::PIC_);
X->InitMCCodeGenInfo(Reloc::PIC_, CM);
return X;
}

6
lib/Target/Blackfin/BlackfinTargetMachine.cpp
View File

@ -24,8 +24,10 @@ extern "C" void LLVMInitializeBlackfinTarget() {
BlackfinTargetMachine::BlackfinTargetMachine(const Target &T,
StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
StringRef FS,
Reloc::Model RM,
CodeModel::Model CM)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
DataLayout("e-p:32:32-i64:32-f64:32-n32"),
Subtarget(TT, CPU, FS),
TLInfo(*this),

3
lib/Target/Blackfin/BlackfinTargetMachine.h
View File

@ -36,7 +36,8 @@ namespace llvm {
BlackfinIntrinsicInfo IntrinsicInfo;
public:
BlackfinTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
virtual const BlackfinInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {

5
lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp
View File

@ -69,9 +69,10 @@ extern "C" void LLVMInitializeBlackfinMCAsmInfo() {
RegisterMCAsmInfo<BlackfinMCAsmInfo> X(TheBlackfinTarget);
}
MCCodeGenInfo *createBlackfinMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *createBlackfinMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM);
X->InitMCCodeGenInfo(RM, CM);
return X;
}

3
lib/Target/CBackend/CTargetMachine.h
View File

@ -21,7 +21,8 @@ namespace llvm {
struct CTargetMachine : public TargetMachine {
CTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM)
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM)
: TargetMachine(T, TT, CPU, FS) {}
virtual bool addPassesToEmitFile(PassManagerBase &PM,

5
lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp
View File

@ -78,11 +78,12 @@ extern "C" void LLVMInitializeCellSPUMCAsmInfo() {
RegisterMCAsmInfoFn X(TheCellSPUTarget, createSPUMCAsmInfo);
}
MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
// For the time being, use static relocations, since there's really no
// support for PIC yet.
X->InitMCCodeGenInfo(Reloc::Static);
X->InitMCCodeGenInfo(Reloc::Static, CM);
return X;
}

5
lib/Target/CellSPU/SPUTargetMachine.cpp
View File

@ -32,8 +32,9 @@ SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const {
}
SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT,
StringRef CPU,StringRef FS, Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
Subtarget(TT, CPU, FS),
DataLayout(Subtarget.getTargetDataString()),
InstrInfo(*this),

3
lib/Target/CellSPU/SPUTargetMachine.h
View File

@ -39,7 +39,8 @@ class SPUTargetMachine : public LLVMTargetMachine {
InstrItineraryData InstrItins;
public:
SPUTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
/// Return the subtarget implementation object
virtual const SPUSubtarget *getSubtargetImpl() const {

3
lib/Target/CppBackend/CPPTargetMachine.h
View File

@ -23,7 +23,8 @@ class formatted_raw_ostream;
struct CPPTargetMachine : public TargetMachine {
CPPTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM)
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM)
: TargetMachine(T, TT, CPU, FS) {}
virtual bool addPassesToEmitFile(PassManagerBase &PM,

7
lib/Target/MBlaze/MBlazeTargetMachine.cpp
View File

@ -68,16 +68,15 @@ extern "C" void LLVMInitializeMBlazeTarget() {
// an easier handling.
MBlazeTargetMachine::
MBlazeTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM):
LLVMTargetMachine(T, TT, CPU, FS, RM),
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM):
LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
Subtarget(TT, CPU, FS),
DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
InstrInfo(*this),
FrameLowering(Subtarget),
TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {
if (getCodeModel() == CodeModel::Default)
setCodeModel(CodeModel::Small);
}
// Install an instruction selector pass using

3
lib/Target/MBlaze/MBlazeTargetMachine.h
View File

@ -42,7 +42,8 @@ namespace llvm {
public:
MBlazeTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
virtual const MBlazeInstrInfo *getInstrInfo() const
{ return &InstrInfo; }

9
lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp
View File

@ -75,11 +75,14 @@ extern "C" void LLVMInitializeMBlazeMCAsmInfo() {
RegisterMCAsmInfoFn X(TheMBlazeTarget, createMCAsmInfo);
}
MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default)
RM = Reloc::Static;
X->InitMCCodeGenInfo(RM);
RM = Reloc::Static;
if (CM == CodeModel::Default)
CM = CodeModel::Small;
X->InitMCCodeGenInfo(RM, CM);
return X;
}

5
lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
View File

@ -67,9 +67,10 @@ extern "C" void LLVMInitializeMSP430MCAsmInfo() {
RegisterMCAsmInfo<MSP430MCAsmInfo> X(TheMSP430Target);
}
MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM);
X->InitMCCodeGenInfo(RM, CM);
return X;
}

5
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -27,8 +27,9 @@ extern "C" void LLVMInitializeMSP430Target() {
MSP430TargetMachine::MSP430TargetMachine(const Target &T,
StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
StringRef FS,
Reloc::Model RM, CodeModel::Model CM)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
Subtarget(TT, CPU, FS),
// FIXME: Check TargetData string.
DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),

3
lib/Target/MSP430/MSP430TargetMachine.h
View File

@ -39,7 +39,8 @@ class MSP430TargetMachine : public LLVMTargetMachine {
public:
MSP430TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
virtual const TargetFrameLowering *getFrameLowering() const {
return &FrameLowering;

5
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
View File

@ -78,7 +78,8 @@ extern "C" void LLVMInitializeMipsMCAsmInfo() {
RegisterMCAsmInfoFn Y(TheMipselTarget, createMipsMCAsmInfo);
}
MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default) {
// Abicall enables PIC by default
@ -88,7 +89,7 @@ MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
else
RM = Reloc::PIC_;
}
X->InitMCCodeGenInfo(RM);
X->InitMCCodeGenInfo(RM, CM);
return X;
}

10
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -32,9 +32,10 @@ extern "C" void LLVMInitializeMipsTarget() {
// Using CodeModel::Large enables different CALL behavior.
MipsTargetMachine::
MipsTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM,
bool isLittle=false):
LLVMTargetMachine(T, TT, CPU, FS, RM),
LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
Subtarget(TT, CPU, FS, isLittle),
DataLayout(isLittle ?
std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
@ -46,8 +47,9 @@ MipsTargetMachine(const Target &T, StringRef TT,
MipselTargetMachine::
MipselTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM) :
MipsTargetMachine(T, TT, CPU, FS, RM, true) {}
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) :
MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {}
// Install an instruction selector pass using
// the ISelDag to gen Mips code.

6
lib/Target/Mips/MipsTargetMachine.h
View File

@ -36,7 +36,8 @@ namespace llvm {
public:
MipsTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool isLittle);
Reloc::Model RM, CodeModel::Model CM,
bool isLittle);
virtual const MipsInstrInfo *getInstrInfo() const
{ return &InstrInfo; }
@ -74,7 +75,8 @@ namespace llvm {
class MipselTargetMachine : public MipsTargetMachine {
public:
MipselTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
};
} // End llvm namespace

5
lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp
View File

@ -71,9 +71,10 @@ extern "C" void LLVMInitializePTXMCAsmInfo() {
RegisterMCAsmInfo<PTXMCAsmInfo> Y(ThePTX64Target);
}
MCCodeGenInfo *createPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *createPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM);
X->InitMCCodeGenInfo(RM, CM);
return X;
}

17
lib/Target/PTX/PTXTargetMachine.cpp
View File

@ -47,11 +47,10 @@ namespace {
// DataLayout and FrameLowering are filled with dummy data
PTXTargetMachine::PTXTargetMachine(const Target &T,
StringRef TT,
StringRef CPU,
StringRef FS,
Reloc::Model RM, bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
StringRef TT, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM,
bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
DataLayout(is64Bit ? DataLayout64 : DataLayout32),
Subtarget(TT, CPU, FS, is64Bit),
FrameLowering(Subtarget),
@ -61,14 +60,14 @@ PTXTargetMachine::PTXTargetMachine(const Target &T,
PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: PTXTargetMachine(T, TT, CPU, FS, RM, false) {
Reloc::Model RM, CodeModel::Model CM)
: PTXTargetMachine(T, TT, CPU, FS, RM, CM, false) {
}
PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: PTXTargetMachine(T, TT, CPU, FS, RM, true) {
Reloc::Model RM, CodeModel::Model CM)
: PTXTargetMachine(T, TT, CPU, FS, RM, CM, true) {
}
bool PTXTargetMachine::addInstSelector(PassManagerBase &PM,

9
lib/Target/PTX/PTXTargetMachine.h
View File

@ -33,7 +33,8 @@ class PTXTargetMachine : public LLVMTargetMachine {
public:
PTXTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM,
bool is64Bit);
virtual const TargetData *getTargetData() const { return &DataLayout; }
@ -62,14 +63,16 @@ class PTX32TargetMachine : public PTXTargetMachine {
public:
PTX32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
}; // class PTX32TargetMachine
class PTX64TargetMachine : public PTXTargetMachine {
public:
PTX64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
}; // class PTX32TargetMachine
} // namespace llvm

5
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
View File

@ -94,7 +94,8 @@ extern "C" void LLVMInitializePowerPCMCAsmInfo() {
RegisterMCAsmInfoFn D(ThePPC64Target, createPPCMCAsmInfo);
}
MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default) {
@ -104,7 +105,7 @@ MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
else
RM = Reloc::Static;
}
X->InitMCCodeGenInfo(RM);
X->InitMCCodeGenInfo(RM, CM);
return X;
}

17
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -54,8 +54,9 @@ extern "C" void LLVMInitializePowerPCTarget() {
PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
Reloc::Model RM, CodeModel::Model CM,
bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
Subtarget(TT, CPU, FS, is64Bit),
DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
FrameLowering(Subtarget), JITInfo(*this, is64Bit),
@ -68,16 +69,16 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: PPCTargetMachine(T, TT, CPU, FS, RM, false) {
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM)
: PPCTargetMachine(T, TT, CPU, FS, RM, CM, false) {
}
PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: PPCTargetMachine(T, TT, CPU, FS, RM, true) {
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM)
: PPCTargetMachine(T, TT, CPU, FS, RM, CM, true) {
}

8
lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -42,7 +42,7 @@ class PPCTargetMachine : public LLVMTargetMachine {
public:
PPCTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool is64Bit);
Reloc::Model RM, CodeModel::Model CM, bool is64Bit);
virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const PPCFrameLowering *getFrameLowering() const {
@ -78,7 +78,8 @@ public:
class PPC32TargetMachine : public PPCTargetMachine {
public:
PPC32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
};
/// PPC64TargetMachine - PowerPC 64-bit target machine.
@ -86,7 +87,8 @@ public:
class PPC64TargetMachine : public PPCTargetMachine {
public:
PPC64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
};
} // end namespace llvm

5
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
View File

@ -66,9 +66,10 @@ extern "C" void LLVMInitializeSparcMCAsmInfo() {
RegisterMCAsmInfo<SparcELFMCAsmInfo> Y(TheSparcV9Target);
}
MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM);
X->InitMCCodeGenInfo(RM, CM);
return X;
}

21
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -26,8 +26,9 @@ extern "C" void LLVMInitializeSparcTarget() {
///
SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool is64bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
Reloc::Model RM, CodeModel::Model CM,
bool is64bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
Subtarget(TT, CPU, FS, is64bit),
DataLayout(Subtarget.getDataLayout()),
TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
@ -51,15 +52,15 @@ bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
}
SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: SparcTargetMachine(T, TT, CPU, FS, RM, false) {
StringRef TT, StringRef CPU,
StringRef FS, Reloc::Model RM,
CodeModel::Model CM)
: SparcTargetMachine(T, TT, CPU, FS, RM, CM, false) {
}
SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: SparcTargetMachine(T, TT, CPU, FS, RM, true) {
StringRef TT, StringRef CPU,
StringRef FS, Reloc::Model RM,
CodeModel::Model CM)
: SparcTargetMachine(T, TT, CPU, FS, RM, CM, true) {
}

8
lib/Target/Sparc/SparcTargetMachine.h
View File

@ -35,7 +35,7 @@ class SparcTargetMachine : public LLVMTargetMachine {
public:
SparcTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool is64bit);
Reloc::Model RM, CodeModel::Model CM, bool is64bit);
virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {
@ -63,7 +63,8 @@ public:
class SparcV8TargetMachine : public SparcTargetMachine {
public:
SparcV8TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
};
/// SparcV9TargetMachine - Sparc 64-bit target machine
@ -71,7 +72,8 @@ public:
class SparcV9TargetMachine : public SparcTargetMachine {
public:
SparcV9TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
};
} // end namespace llvm

5
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
View File

@ -68,11 +68,12 @@ extern "C" void LLVMInitializeSystemZMCAsmInfo() {
RegisterMCAsmInfo<SystemZMCAsmInfo> X(TheSystemZTarget);
}
MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default)
RM = Reloc::Static;
X->InitMCCodeGenInfo(RM);
X->InitMCCodeGenInfo(RM, CM);
return X;
}

8
lib/Target/SystemZ/SystemZTargetMachine.cpp
View File

@ -21,10 +21,10 @@ extern "C" void LLVMInitializeSystemZTarget() {
/// SystemZTargetMachine ctor - Create an ILP64 architecture model
///
SystemZTargetMachine::SystemZTargetMachine(const Target &T,
StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
StringRef TT, StringRef CPU,
StringRef FS, Reloc::Model RM,
CodeModel::Model CM)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
Subtarget(TT, CPU, FS),
DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
"-f64:64:64-f128:128:128-a0:16:16-n32:64"),

3
lib/Target/SystemZ/SystemZTargetMachine.h
View File

@ -38,7 +38,8 @@ class SystemZTargetMachine : public LLVMTargetMachine {
SystemZFrameLowering FrameLowering;
public:
SystemZTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
virtual const TargetFrameLowering *getFrameLowering() const {
return &FrameLowering;

29
lib/Target/TargetMachine.cpp
View File

@ -40,7 +40,6 @@ namespace llvm {
bool JITExceptionHandling;
bool JITEmitDebugInfo;
bool JITEmitDebugInfoToDisk;
CodeModel::Model CMModel;
bool GuaranteedTailCallOpt;
unsigned StackAlignmentOverride;
bool RealignStack;
@ -142,23 +141,6 @@ EmitJitDebugInfoToDisk("jit-emit-debug-to-disk",
cl::location(JITEmitDebugInfoToDisk),
cl::init(false));
static cl::opt<llvm::CodeModel::Model, true>
DefCodeModel("code-model",
cl::desc("Choose code model"),
cl::location(CMModel),
cl::init(CodeModel::Default),
cl::values(
clEnumValN(CodeModel::Default, "default",
"Target default code model"),
clEnumValN(CodeModel::Small, "small",
"Small code model"),
clEnumValN(CodeModel::Kernel, "kernel",
"Kernel code model"),
clEnumValN(CodeModel::Medium, "medium",
"Medium code model"),
clEnumValN(CodeModel::Large, "large",
"Large code model"),
clEnumValEnd));
static cl::opt<bool, true>
EnableGuaranteedTailCallOpt("tailcallopt",
cl::desc("Turn fastcc calls into tail calls by (potentially) changing ABI."),
@ -230,13 +212,10 @@ Reloc::Model TargetMachine::getRelocationModel() const {
/// getCodeModel - Returns the code model. The choices are small, kernel,
/// medium, large, and target default.
CodeModel::Model TargetMachine::getCodeModel() {
return CMModel;
}
/// setCodeModel - Sets the code model.
void TargetMachine::setCodeModel(CodeModel::Model Model) {
CMModel = Model;
CodeModel::Model TargetMachine::getCodeModel() const {
if (!CodeGenInfo)
return CodeModel::Default;
return CodeGenInfo->getCodeModel();
}
bool TargetMachine::getAsmVerbosityDefault() {

12
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
View File

@ -339,7 +339,8 @@ extern "C" void LLVMInitializeX86MCAsmInfo() {
RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
}
MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
Triple T(TT);
@ -376,7 +377,14 @@ MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM) {
if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
RM = Reloc::PIC_;
X->InitMCCodeGenInfo(RM);
// For static codegen, if we're not already set, use Small codegen.
if (CM == CodeModel::Default)
CM = CodeModel::Small;
else if (CM == CodeModel::JITDefault)
// 64-bit JIT places everything in the same buffer except external funcs.
CM = is64Bit ? CodeModel::Large : CodeModel::Small;
X->InitMCCodeGenInfo(RM, CM);
return X;
}

33
lib/Target/X86/X86TargetMachine.cpp
View File

@ -67,8 +67,8 @@ extern "C" void LLVMInitializeX86Target() {
X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: X86TargetMachine(T, TT, CPU, FS, RM, false),
Reloc::Model RM, CodeModel::Model CM)
: X86TargetMachine(T, TT, CPU, FS, RM, CM, false),
DataLayout(getSubtargetImpl()->isTargetDarwin() ?
"e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-n8:16:32" :
(getSubtargetImpl()->isTargetCygMing() ||
@ -84,8 +84,8 @@ X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: X86TargetMachine(T, TT, CPU, FS, RM, true),
Reloc::Model RM, CodeModel::Model CM)
: X86TargetMachine(T, TT, CPU, FS, RM, CM, true),
DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-n8:16:32:64"),
InstrInfo(*this),
TSInfo(*this),
@ -97,8 +97,9 @@ X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
///
X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
Reloc::Model RM, CodeModel::Model CM,
bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit),
FrameLowering(*this, Subtarget),
ELFWriterInfo(is64Bit, true) {
@ -171,23 +172,3 @@ bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
return false;
}
void X86TargetMachine::setCodeModelForStatic() {
if (getCodeModel() != CodeModel::Default) return;
// For static codegen, if we're not already set, use Small codegen.
setCodeModel(CodeModel::Small);
}
void X86TargetMachine::setCodeModelForJIT() {
if (getCodeModel() != CodeModel::Default) return;
// 64-bit JIT places everything in the same buffer except external functions.
if (Subtarget.is64Bit())
setCodeModel(CodeModel::Large);
else
setCodeModel(CodeModel::Small);
}

14
lib/Target/X86/X86TargetMachine.h
View File

@ -36,15 +36,11 @@ class X86TargetMachine : public LLVMTargetMachine {
X86FrameLowering FrameLowering;
X86ELFWriterInfo ELFWriterInfo;
private:
// We have specific defaults for X86.
virtual void setCodeModelForJIT();
virtual void setCodeModelForStatic();
public:
X86TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool is64Bit);
Reloc::Model RM, CodeModel::Model CM,
bool is64Bit);
virtual const X86InstrInfo *getInstrInfo() const {
llvm_unreachable("getInstrInfo not implemented");
@ -88,7 +84,8 @@ class X86_32TargetMachine : public X86TargetMachine {
X86JITInfo JITInfo;
public:
X86_32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual const X86TargetLowering *getTargetLowering() const {
return &TLInfo;
@ -114,7 +111,8 @@ class X86_64TargetMachine : public X86TargetMachine {
X86JITInfo JITInfo;
public:
X86_64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual const X86TargetLowering *getTargetLowering() const {
return &TLInfo;

5
lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
View File

@ -76,9 +76,10 @@ extern "C" void LLVMInitializeXCoreMCAsmInfo() {
RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo);
}
MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM);
X->InitMCCodeGenInfo(RM, CM);
return X;
}

6
lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -20,9 +20,9 @@ using namespace llvm;
/// XCoreTargetMachine ctor - Create an ILP32 architecture model
///
XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
Subtarget(TT, CPU, FS),
DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
"i16:16:32-i32:32:32-i64:32:32-n32"),

3
lib/Target/XCore/XCoreTargetMachine.h
View File

@ -33,7 +33,8 @@ class XCoreTargetMachine : public LLVMTargetMachine {
XCoreSelectionDAGInfo TSInfo;
public:
XCoreTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const XCoreFrameLowering *getFrameLowering() const {

21
tools/llc/llc.cpp
View File

@ -91,6 +91,22 @@ RelocModel("relocation-model",
"Relocatable external references, non-relocatable code"),
clEnumValEnd));
static cl::opt<llvm::CodeModel::Model>
CMModel("code-model",
cl::desc("Choose code model"),
cl::init(CodeModel::Default),
cl::values(clEnumValN(CodeModel::Default, "default",
"Target default code model"),
clEnumValN(CodeModel::Small, "small",
"Small code model"),
clEnumValN(CodeModel::Kernel, "kernel",
"Kernel code model"),
clEnumValN(CodeModel::Medium, "medium",
"Medium code model"),
clEnumValN(CodeModel::Large, "large",
"Large code model"),
clEnumValEnd));
static cl::opt<bool>
RelaxAll("mc-relax-all",
cl::desc("When used with filetype=obj, "
@ -287,8 +303,9 @@ int main(int argc, char **argv) {
}
std::auto_ptr<TargetMachine>
target(TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU,
FeaturesStr, RelocModel));
target(TheTarget->createTargetMachine(TheTriple.getTriple(),
MCPU, FeaturesStr,
RelocModel, CMModel));
assert(target.get() && "Could not allocate target machine!");
TargetMachine &Target = *target.get();

18
tools/lli/lli.cpp
View File

@ -123,6 +123,23 @@ namespace {
clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
"Relocatable external references, non-relocatable code"),
clEnumValEnd));
cl::opt<llvm::CodeModel::Model>
CMModel("code-model",
cl::desc("Choose code model"),
cl::init(CodeModel::JITDefault),
cl::values(clEnumValN(CodeModel::JITDefault, "default",
"Target default JIT code model"),
clEnumValN(CodeModel::Small, "small",
"Small code model"),
clEnumValN(CodeModel::Kernel, "kernel",
"Kernel code model"),
clEnumValN(CodeModel::Medium, "medium",
"Medium code model"),
clEnumValN(CodeModel::Large, "large",
"Large code model"),
clEnumValEnd));
}
static ExecutionEngine *EE = 0;
@ -180,6 +197,7 @@ int main(int argc, char **argv, char * const *envp) {
builder.setMCPU(MCPU);
builder.setMAttrs(MAttrs);
builder.setRelocationModel(RelocModel);
builder.setCodeModel(CMModel);
builder.setErrorStr(&ErrorMsg);
builder.setEngineKind(ForceInterpreter
? EngineKind::Interpreter

19
tools/llvm-mc/llvm-mc.cpp
View File

@ -128,6 +128,22 @@ RelocModel("relocation-model",
"Relocatable external references, non-relocatable code"),
clEnumValEnd));
static cl::opt<llvm::CodeModel::Model>
CMModel("code-model",
cl::desc("Choose code model"),
cl::init(CodeModel::Default),
cl::values(clEnumValN(CodeModel::Default, "default",
"Target default code model"),
clEnumValN(CodeModel::Small, "small",
"Small code model"),
clEnumValN(CodeModel::Kernel, "kernel",
"Kernel code model"),
clEnumValN(CodeModel::Medium, "medium",
"Medium code model"),
clEnumValN(CodeModel::Large, "large",
"Large code model"),
clEnumValEnd));
static cl::opt<bool>
NoInitialTextSection("n", cl::desc("Don't assume assembly file starts "
"in the text section"));
@ -339,7 +355,8 @@ static int AssembleInput(const char *ProgName) {
OwningPtr<TargetMachine> TM(TheTarget->createTargetMachine(TripleName,
MCPU,
FeaturesStr,
RelocModel));
RelocModel,
CMModel));
if (!TM) {
errs() << ProgName << ": error: could not create target for triple '"