mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-12 06:06:19 +00:00
R600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VI
These are VOP3-only on VI. The new multiclass doesn't define VOP3 versions of VOP2 instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226189 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
6589ea14e7
commit
352fa59ec3
@ -998,6 +998,23 @@ multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
|
||||
}
|
||||
}
|
||||
|
||||
// An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
|
||||
multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
|
||||
string asm, list<dag> pattern = []> {
|
||||
let isPseudo = 1 in {
|
||||
def "" : VOPAnyCommon <outs, ins, "", pattern>,
|
||||
SIMCInstr<opName, SISubtarget.NONE>;
|
||||
}
|
||||
|
||||
def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
|
||||
SIMCInstr <opName, SISubtarget.SI>;
|
||||
|
||||
def _vi : VOP3Common <outs, ins, asm, []>,
|
||||
VOP3e_vi <op.VI3>,
|
||||
VOP3DisableFields <1, 0, 0>,
|
||||
SIMCInstr <opName, SISubtarget.VI>;
|
||||
}
|
||||
|
||||
multiclass VOP1_Helper <vop1 op, string opName, dag outs,
|
||||
dag ins32, string asm32, list<dag> pat32,
|
||||
dag ins64, string asm64, list<dag> pat64,
|
||||
|
@ -1525,25 +1525,25 @@ defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32",
|
||||
} // End Uses = [VCC]
|
||||
} // End isCommutable = 1, Defs = [VCC]
|
||||
|
||||
// These instructions only exist on SI and CI
|
||||
let SubtargetPredicate = isSICI in {
|
||||
|
||||
def V_READLANE_B32 : VOP2 <
|
||||
0x00000001,
|
||||
defm V_READLANE_B32 : VOP2SI_3VI_m <
|
||||
vop3 <0x001, 0x289>,
|
||||
"v_readlane_b32",
|
||||
(outs SReg_32:$vdst),
|
||||
(ins VGPR_32:$src0, SSrc_32:$vsrc1),
|
||||
"v_readlane_b32 $vdst, $src0, $vsrc1",
|
||||
[]
|
||||
"v_readlane_b32 $vdst, $src0, $vsrc1"
|
||||
>;
|
||||
|
||||
def V_WRITELANE_B32 : VOP2 <
|
||||
0x00000002,
|
||||
defm V_WRITELANE_B32 : VOP2SI_3VI_m <
|
||||
vop3 <0x002, 0x28a>,
|
||||
"v_writelane_b32",
|
||||
(outs VGPR_32:$vdst),
|
||||
(ins SReg_32:$src0, SSrc_32:$vsrc1),
|
||||
"v_writelane_b32 $vdst, $src0, $vsrc1",
|
||||
[]
|
||||
"v_writelane_b32 $vdst, $src0, $vsrc1"
|
||||
>;
|
||||
|
||||
// These instructions only exist on SI and CI
|
||||
let SubtargetPredicate = isSICI in {
|
||||
|
||||
let isCommutable = 1 in {
|
||||
defm V_MAC_LEGACY_F32 : VOP2Inst <vop2<0x6>, "v_mac_legacy_f32",
|
||||
VOP_F32_F32_F32
|
||||
|
Loading…
Reference in New Issue
Block a user