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FTOIT and ITOFT are bit converts, and if we drop 21264s, are always available

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33492 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2007-01-24 21:09:16 +00:00
parent 0e41094d49
commit 3553d86731
8 changed files with 17 additions and 73 deletions
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8
lib/Target/Alpha/Alpha.td
View File

@ -22,8 +22,6 @@ include "../Target.td"
def FeatureCIX : SubtargetFeature<"CIX", "HasCT", "true",
"Enable CIX extentions">;
def FeatureFIX : SubtargetFeature<"FIX", "HasF2I", "true",
"Enable FIX extentions">;
//===----------------------------------------------------------------------===//
// Register File Description
@ -54,10 +52,8 @@ def AlphaInstrInfo : InstrInfo {
//===----------------------------------------------------------------------===//
def : Processor<"generic", Alpha21264Itineraries, []>;
def : Processor<"pca56" , Alpha21264Itineraries, []>;
def : Processor<"ev56" , Alpha21264Itineraries, []>;
def : Processor<"ev6" , Alpha21264Itineraries, [FeatureFIX]>;
def : Processor<"ev67" , Alpha21264Itineraries, [FeatureFIX, FeatureCIX]>;
def : Processor<"ev6" , Alpha21264Itineraries, []>;
def : Processor<"ev67" , Alpha21264Itineraries, [FeatureCIX]>;
//===----------------------------------------------------------------------===//
// The Alpha Target

7
lib/Target/Alpha/AlphaAsmPrinter.cpp
View File

@ -190,11 +190,10 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
bool AlphaAsmPrinter::doInitialization(Module &M)
{
AsmPrinter::doInitialization(M);
if(TM.getSubtarget<AlphaSubtarget>().hasF2I()
|| TM.getSubtarget<AlphaSubtarget>().hasCT())
O << "\t.arch ev6\n";
if(TM.getSubtarget<AlphaSubtarget>().hasCT())
O << "\t.arch ev6\n"; //This might need to be ev67, so leave this test here
else
O << "\t.arch ev56\n";
O << "\t.arch ev6\n";
O << "\t.set noat\n";
return false;
}

35
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -394,24 +394,10 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
default: break;
}
SDOperand LD;
if (AlphaLowering.hasITOF()) {
LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
} else {
int FrameIdx =
CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
SDOperand ST =
SDOperand(CurDAG->getTargetNode(Alpha::STT, MVT::Other,
SDOperand(cmp, 0), FI,
CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
LD = SDOperand(CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
CurDAG->getRegister(Alpha::R31, MVT::i64),
ST), 0);
}
SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDOperand(cmp, 0));
return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
CurDAG->getRegister(Alpha::R31, MVT::i64),
LD);
SDOperand(LD,0));
}
break;
@ -424,7 +410,6 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
// so that things like this can be caught in fall though code
//move int to fp
bool isDouble = N->getValueType(0) == MVT::f64;
SDOperand LD;
SDOperand cond = N->getOperand(0);
SDOperand TV = N->getOperand(1);
SDOperand FV = N->getOperand(2);
@ -432,21 +417,9 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
AddToISelQueue(TV);
AddToISelQueue(FV);
if (AlphaLowering.hasITOF()) {
LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
} else {
int FrameIdx =
CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
SDOperand ST =
SDOperand(CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
LD = SDOperand(CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
CurDAG->getRegister(Alpha::R31, MVT::i64),
ST), 0);
}
SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond);
return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
MVT::f64, FV, TV, LD);
MVT::f64, FV, TV, SDOperand(LD,0));
}
break;

27
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -104,6 +104,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
setOperationAction(ISD::SETCC, MVT::f32, Promote);
setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
@ -143,15 +145,11 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
setJumpBufAlignment(16);
computeRegisterProperties();
useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
}
const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default: return 0;
case AlphaISD::ITOFT_: return "Alpha::ITOFT_";
case AlphaISD::FTOIT_: return "Alpha::FTOIT_";
case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
@ -398,16 +396,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
"Unhandled SINT_TO_FP type in custom expander!");
SDOperand LD;
bool isDouble = MVT::f64 == Op.getValueType();
if (useITOF) {
LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
} else {
int FrameIdx =
DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
SDOperand ST = DAG.getStore(DAG.getEntryNode(),
Op.getOperand(0), FI, NULL, 0);
LD = DAG.getLoad(MVT::f64, ST, FI, NULL, 0);
}
LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
isDouble?MVT::f64:MVT::f32, LD);
return FP;
@ -421,15 +410,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
if (useITOF) {
return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
} else {
int FrameIdx =
DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
SDOperand ST = DAG.getStore(DAG.getEntryNode(), src, FI, NULL, 0);
return DAG.getLoad(MVT::i64, ST, FI, NULL, 0);
}
return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src);
}
case ISD::ConstantPool: {
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);

2
lib/Target/Alpha/AlphaISelLowering.h
View File

@ -27,7 +27,7 @@ namespace llvm {
// Start the numbering where the builting ops and target ops leave off.
FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END,
//These corrospond to the identical Instruction
ITOFT_, FTOIT_, CVTQT_, CVTQS_, CVTTQ_,
CVTQT_, CVTQS_, CVTTQ_,
/// GPRelHi/GPRelLo - These represent the high and low 16-bit
/// parts of a global address respectively.

6
lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -19,8 +19,6 @@ include "AlphaInstrFormats.td"
def SDTFPUnaryOpUnC : SDTypeProfile<1, 1, [
SDTCisFP<1>, SDTCisFP<0>
]>;
def Alpha_itoft : SDNode<"AlphaISD::ITOFT_", SDTIntToFPOp, []>;
def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_" , SDTFPUnaryOp, []>;
@ -745,12 +743,12 @@ let OperandList = (ops GPRC:$RC, F4RC:$RA), Fb = 31 in
def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC",[], s_ftoi>; //Floating to integer move, S_floating
let OperandList = (ops GPRC:$RC, F8RC:$RA), Fb = 31 in
def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC",
[(set GPRC:$RC, (Alpha_ftoit F8RC:$RA))], s_ftoi>; //Floating to integer move
[(set GPRC:$RC, (bitconvert F8RC:$RA))], s_ftoi>; //Floating to integer move
let OperandList = (ops F4RC:$RC, GPRC:$RA), Fb = 31 in
def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC",[], s_itof>; //Integer to floating move, S_floating
let OperandList = (ops F8RC:$RC, GPRC:$RA), Fb = 31 in
def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC",
[(set F8RC:$RC, (Alpha_itoft GPRC:$RA))], s_itof>; //Integer to floating move
[(set F8RC:$RC, (bitconvert GPRC:$RA))], s_itof>; //Integer to floating move
let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in

2
lib/Target/Alpha/AlphaSubtarget.cpp
View File

@ -17,7 +17,7 @@
using namespace llvm;
AlphaSubtarget::AlphaSubtarget(const Module &M, const std::string &FS)
: HasF2I(false), HasCT(false) {
: HasCT(false) {
std::string CPU = "generic";
// Parse features string.

3
lib/Target/Alpha/AlphaSubtarget.h
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@ -25,8 +25,6 @@ class Module;
class AlphaSubtarget : public TargetSubtarget {
protected:
/// Used by the ISel to turn in optimizations for POWER4-derived architectures
bool HasF2I;
bool HasCT;
InstrItineraryData InstrItins;
@ -41,7 +39,6 @@ public:
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
bool hasF2I() const { return HasF2I; }
bool hasCT() const { return HasCT; }
};
} // End llvm namespace