RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-01-23 20:57:21 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

R600/SI: Fix broken check lines.

Browse Source 
Fix missing check, and hardcoded register numbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217318 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-09-06 20:37:56 +00:00
parent 5f61134595
commit 360ed46f68
2 changed files with 7 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
test/CodeGen/R600/smrd.ll
View File

@ -26,6 +26,7 @@ entry:
; CHECK-LABEL: @smrd2
; CHECK: S_MOV_B32 s[[OFFSET:[0-9]]], 0x400
; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
; CHECK: S_ENDPGM
define void @smrd2(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
entry:
%0 = getelementptr i32 addrspace(2)* %ptr, i64 256
@ -36,14 +37,14 @@ entry:
; SMRD load with a 64-bit offset
; CHECK-LABEL: @smrd3
; CHECK-DAG: S_MOV_B32 s[[SHI:[0-9]+]], 4
; CHECK-DAG: S_MOV_B32 s[[SLO:[0-9]+]], 0
; CHECK-DAG: S_MOV_B32 s[[SHI:[0-9]+]], 4
; FIXME: We don't need to copy these values to VGPRs
; CHECK-DAG: V_MOV_B32_e32 v[[VHI:[0-9]+]], s[[SHI]]
; CHECK-DAG: V_MOV_B32_e32 v[[VLO:[0-9]+]], s[[SLO]]
; FIXME: We should be able to use S_LOAD_DWORD here
; BUFFER_LOAD_DWORD v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}] + v[[[VLO]]:[[VHI]]] + 0x0
; CHECK: BUFFER_LOAD_DWORD v{{[0-9]+}}, v{{\[}}[[VLO]]:[[VHI]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0
; CHECK: S_ENDPGM
define void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
entry:
%0 = getelementptr i32 addrspace(2)* %ptr, i64 4294967296 ; 2 ^ 32

6
test/CodeGen/R600/trunc.ll
View File

@ -3,9 +3,9 @@
define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {
; SI-LABEL: @trunc_i64_to_i32_store
; SI: S_LOAD_DWORD s0, s[0:1], 0xb
; SI: V_MOV_B32_e32 v0, s0
; SI: BUFFER_STORE_DWORD v0
; SI: S_LOAD_DWORD [[SLOAD:s[0-9]+]], s[0:1], 0xb
; SI: V_MOV_B32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]
; SI: BUFFER_STORE_DWORD [[VLOAD]]
; EG-LABEL: @trunc_i64_to_i32_store
; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1