From 36229b4631a62dc97d546268f4e4d11c43afcfa1 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 21 Feb 2017 22:50:41 +0000 Subject: [PATCH] AMDGPU: Formatting fixes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295783 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIISelLowering.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index b0410b56cf3..60acf4fb1c0 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1533,11 +1533,12 @@ static bool setM0ToIndexFromSGPR(const SIInstrInfo *TII, } if (Offset == 0) { - BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0).add(*Idx); + BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) + .add(*Idx); } else { BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0) - .add(*Idx) - .addImm(Offset); + .add(*Idx) + .addImm(Offset); } return true; @@ -2872,7 +2873,7 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, unsigned IntrinsicID = cast(Op.getOperand(1))->getZExtValue(); switch (IntrinsicID) { - case Intrinsic::amdgcn_exp: { + case Intrinsic::amdgcn_exp: { const ConstantSDNode *Tgt = cast(Op.getOperand(2)); const ConstantSDNode *En = cast(Op.getOperand(3)); const ConstantSDNode *Done = cast(Op.getOperand(8));