RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-27 21:50:40 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[AArch64] Fix assertion failure caused by an invalid comparison between APInt values.

Browse Source 
APInt only knows how to compare values with the same BitWidth and asserts
in all other cases.

With this fix, function PerformORCombine does not use the APInt equality
operator if the APInt values returned by 'isConstantSplat' differ in BitWidth.
In that case they are different and no comparison is needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199119 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio 2014-01-13 16:51:00 +00:00
parent 286cc13546
commit 36713c2c0a
2 changed files with 32 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -3476,8 +3476,9 @@ static SDValue PerformORCombine(SDNode *N,
BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
APInt SplatBits1;
if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
HasAnyUndefs) &&
!HasAnyUndefs && SplatBits0 == ~SplatBits1) {
HasAnyUndefs) && !HasAnyUndefs &&
SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
SplatBits0 == ~SplatBits1) {
return DAG.getNode(ISD::VSELECT, DL, VT, N0->getOperand(1),
N0->getOperand(0), N1->getOperand(0));

29
test/CodeGen/AArch64/neon-or-combine.ll Normal file
View File

@ -0,0 +1,29 @@
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
; Check that the DAGCombiner does not crash with an assertion failure
; when performing a target specific combine to simplify a 'or' dag node
; according to the following rule:
; (or (and B, A), (and C, ~A)) => (VBSL A, B, C)
; The assertion failure was caused by an invalid comparison between APInt
; values with different 'BitWidth'.
define <8 x i8> @test1(<8 x i8> %a, <8 x i8> %b) {
%tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0 >
%tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0 >
%tmp3 = or <8 x i8> %tmp1, %tmp2
ret <8 x i8> %tmp3
}
; CHECK-LABEL: test1
; CHECK: ret
define <16 x i8> @test2(<16 x i8> %a, <16 x i8> %b) {
%tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp2 = and <16 x i8> %b, < i8 -1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0 >
%tmp3 = or <16 x i8> %tmp1, %tmp2
ret <16 x i8> %tmp3
}
; CHECK-LABEL: test2
; CHECK: ret