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[AArch32] Add patterns for VCVT{A,N,P,M}.
Patterns for lowering libm calls to VCVT{A,N,P,M} are also included.
Phabricator Revision: http://reviews.llvm.org/D5033
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216388 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
parent
cc4b123a47
commit
373fc00835
@ -627,27 +627,30 @@ def : Pat<(f16_to_fp GPR:$a),
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def : Pat<(f64 (f16_to_fp GPR:$a)),
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(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
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multiclass vcvt_inst<string opc, bits<2> rm> {
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multiclass vcvt_inst<string opc, bits<2> rm,
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SDPatternOperator node = null_frag> {
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let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
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def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
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(outs SPR:$Sd), (ins SPR:$Sm),
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NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
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[]>, Requires<[HasFPARMv8]> {
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[(set SPR:$Sd, (arm_ftosi (node SPR:$Sm)))]>,
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Requires<[HasFPARMv8]> {
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let Inst{17-16} = rm;
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}
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def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
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(outs SPR:$Sd), (ins SPR:$Sm),
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NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
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[]>, Requires<[HasFPARMv8]> {
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[(set SPR:$Sd, (arm_ftoui (node SPR:$Sm)))]>,
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Requires<[HasFPARMv8]> {
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let Inst{17-16} = rm;
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}
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def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
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(outs SPR:$Sd), (ins DPR:$Dm),
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NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
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[]>, Requires<[HasFPARMv8, HasDPVFP]> {
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[(set SPR:$Sd, (arm_ftosi (f64 (node (f64 DPR:$Dm)))))]>,
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Requires<[HasFPARMv8, HasDPVFP]> {
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bits<5> Dm;
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let Inst{17-16} = rm;
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@ -661,7 +664,8 @@ multiclass vcvt_inst<string opc, bits<2> rm> {
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def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
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(outs SPR:$Sd), (ins DPR:$Dm),
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NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
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[]>, Requires<[HasFPARMv8, HasDPVFP]> {
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[(set SPR:$Sd, (arm_ftoui (f64 (node (f64 DPR:$Dm)))))]>,
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Requires<[HasFPARMv8, HasDPVFP]> {
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bits<5> Dm;
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let Inst{17-16} = rm;
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@ -674,10 +678,10 @@ multiclass vcvt_inst<string opc, bits<2> rm> {
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}
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}
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defm VCVTA : vcvt_inst<"a", 0b00>;
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defm VCVTA : vcvt_inst<"a", 0b00, frnd>;
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defm VCVTN : vcvt_inst<"n", 0b01>;
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defm VCVTP : vcvt_inst<"p", 0b10>;
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defm VCVTM : vcvt_inst<"m", 0b11>;
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defm VCVTP : vcvt_inst<"p", 0b10, fceil>;
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defm VCVTM : vcvt_inst<"m", 0b11, ffloor>;
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def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
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(outs DPR:$Dd), (ins DPR:$Dm),
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117
test/CodeGen/ARM/arm32-round-conv.ll
Normal file
117
test/CodeGen/ARM/arm32-round-conv.ll
Normal file
@ -0,0 +1,117 @@
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; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+fp-armv8 | FileCheck %s
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; RUN: llc < %s -mtriple=armv8-linux-gnueabihf -mattr=+fp-armv8 | FileCheck %s
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; CHECK-LABEL: test1
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; CHECK: vcvtm.s32.f32
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define i32 @test1(float %a) {
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entry:
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%call = call float @floorf(float %a) nounwind readnone
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%conv = fptosi float %call to i32
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ret i32 %conv
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}
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; CHECK-LABEL: test2
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; CHECK: vcvtm.u32.f32
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define i32 @test2(float %a) {
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entry:
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%call = call float @floorf(float %a) nounwind readnone
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%conv = fptoui float %call to i32
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ret i32 %conv
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}
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; CHECK-LABEL: test3
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; CHECK: vcvtm.s32.f64
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define i32 @test3(double %a) {
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entry:
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%call = call double @floor(double %a) nounwind readnone
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%conv = fptosi double %call to i32
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ret i32 %conv
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}
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; CHECK-LABEL: test4
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; CHECK: vcvtm.u32.f64
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define i32 @test4(double %a) {
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entry:
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%call = call double @floor(double %a) nounwind readnone
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%conv = fptoui double %call to i32
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ret i32 %conv
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}
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; CHECK-LABEL: test5
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; CHECK: vcvtp.s32.f32
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define i32 @test5(float %a) {
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entry:
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%call = call float @ceilf(float %a) nounwind readnone
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%conv = fptosi float %call to i32
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ret i32 %conv
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}
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; CHECK-LABEL: test6
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; CHECK: vcvtp.u32.f32
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define i32 @test6(float %a) {
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entry:
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%call = call float @ceilf(float %a) nounwind readnone
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%conv = fptoui float %call to i32
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ret i32 %conv
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}
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; CHECK-LABEL: test7
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; CHECK: vcvtp.s32.f64
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define i32 @test7(double %a) {
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entry:
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%call = call double @ceil(double %a) nounwind readnone
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%conv = fptosi double %call to i32
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ret i32 %conv
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}
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; CHECK-LABEL: test8
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; CHECK: vcvtp.u32.f64
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define i32 @test8(double %a) {
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entry:
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%call = call double @ceil(double %a) nounwind readnone
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%conv = fptoui double %call to i32
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ret i32 %conv
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}
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; CHECK-LABEL: test9
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; CHECK: vcvta.s32.f32
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define i32 @test9(float %a) {
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entry:
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%call = call float @roundf(float %a) nounwind readnone
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%conv = fptosi float %call to i32
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ret i32 %conv
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}
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; CHECK-LABEL: test10
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; CHECK: vcvta.u32.f32
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define i32 @test10(float %a) {
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entry:
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%call = call float @roundf(float %a) nounwind readnone
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%conv = fptoui float %call to i32
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ret i32 %conv
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}
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; CHECK-LABEL: test11
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; CHECK: vcvta.s32.f64
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define i32 @test11(double %a) {
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entry:
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%call = call double @round(double %a) nounwind readnone
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%conv = fptosi double %call to i32
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ret i32 %conv
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}
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; CHECK-LABEL: test12
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; CHECK: vcvta.u32.f64
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define i32 @test12(double %a) {
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entry:
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%call = call double @round(double %a) nounwind readnone
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%conv = fptoui double %call to i32
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ret i32 %conv
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}
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declare float @floorf(float) nounwind readnone
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declare double @floor(double) nounwind readnone
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declare float @ceilf(float) nounwind readnone
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declare double @ceil(double) nounwind readnone
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declare float @roundf(float) nounwind readnone
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declare double @round(double) nounwind readnone
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