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test/CodeGen/X86: Add a pattern for Win64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127733 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
NAKAMURA Takumi
parent
ddbfbcf72e
commit
37947c6bad
@ -1,10 +1,16 @@
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; RUN: llc < %s -o - -march=x86-64 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=WIN64
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; PR8573
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; CHECK: foo:
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; CHECK: leaq (%rdi), %rax
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: monitor
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; WIN64: foo:
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; WIN64: leaq (%rcx), %rax
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; WIN64-NEXT: movl %edx, %ecx
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; WIN64-NEXT: movl %r8d, %edx
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; WIN64-NEXT: monitor
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define void @foo(i8* %P, i32 %E, i32 %H) nounwind {
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entry:
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tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H)
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@ -17,6 +23,9 @@ declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind
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; CHECK: movl %edi, %ecx
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: mwait
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; WIN64: bar:
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; WIN64: movl %edx, %eax
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; WIN64-NEXT: mwait
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define void @bar(i32 %E, i32 %H) nounwind {
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entry:
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tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H)
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@ -1,9 +1,29 @@
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; RUN: llc < %s -march=x86-64 > %t
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; RUN: grep mov %t | count 6
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; RUN: grep {movb %ah, (%rsi)} %t | count 3
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; RUN: llc < %s -march=x86 > %t
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; RUN: grep mov %t | count 3
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; RUN: grep {movb %ah, (%e} %t | count 3
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64
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; X64: mov
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; X64-NEXT: movb %ah, (%rsi)
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; X64: mov
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; X64-NEXT: movb %ah, (%rsi)
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; X64: mov
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; X64-NEXT: movb %ah, (%rsi)
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; X64-NOT: mov
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; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=W64
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; W64-NOT: mov
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; W64: movb %ch, (%rdx)
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; W64-NOT: mov
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; W64: movb %ch, (%rdx)
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; W64-NOT: mov
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; W64: movb %ch, (%rdx)
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; W64-NOT: mov
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; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32
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; X32-NOT: mov
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; X32: movb %ah, (%e
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; X32-NOT: mov
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; X32: movb %ah, (%e
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; X32-NOT: mov
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; X32: movb %ah, (%e
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; X32-NOT: mov
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; Use h-register extract and store.
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@ -1,4 +1,5 @@
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; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X86-64
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X86-64
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; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=WIN64
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; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X86-32
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; Use h registers. On x86-64, codegen doesn't support general allocation
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@ -9,6 +10,12 @@ define void @bar64(i64 inreg %x, i8* inreg %p) nounwind {
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; X86-64: shrq $8, %rdi
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; X86-64: incb %dil
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; See FIXME: on regclass GR8.
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; It could be optimally transformed like; incb %ch; movb %ch, (%rdx)
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; WIN64: bar64:
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; WIN64: shrq $8, %rcx
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; WIN64: incb %cl
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; X86-32: bar64:
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; X86-32: incb %ah
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%t0 = lshr i64 %x, 8
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@ -23,6 +30,10 @@ define void @bar32(i32 inreg %x, i8* inreg %p) nounwind {
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; X86-64: shrl $8, %edi
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; X86-64: incb %dil
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; WIN64: bar32:
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; WIN64: shrl $8, %ecx
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; WIN64: incb %cl
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; X86-32: bar32:
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; X86-32: incb %ah
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%t0 = lshr i32 %x, 8
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@ -37,6 +48,10 @@ define void @bar16(i16 inreg %x, i8* inreg %p) nounwind {
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; X86-64: shrl $8, %edi
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; X86-64: incb %dil
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; WIN64: bar16:
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; WIN64: shrl $8, %ecx
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; WIN64: incb %cl
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; X86-32: bar16:
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; X86-32: incb %ah
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%t0 = lshr i16 %x, 8
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@ -51,6 +66,9 @@ define i64 @qux64(i64 inreg %x) nounwind {
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; X86-64: movq %rdi, %rax
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; X86-64: movzbl %ah, %eax
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; WIN64: qux64:
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; WIN64: movzbl %ch, %eax
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; X86-32: qux64:
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; X86-32: movzbl %ah, %eax
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%t0 = lshr i64 %x, 8
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@ -63,6 +81,9 @@ define i32 @qux32(i32 inreg %x) nounwind {
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; X86-64: movl %edi, %eax
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; X86-64: movzbl %ah, %eax
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; WIN64: qux32:
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; WIN64: movzbl %ch, %eax
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; X86-32: qux32:
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; X86-32: movzbl %ah, %eax
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%t0 = lshr i32 %x, 8
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@ -75,6 +96,9 @@ define i16 @qux16(i16 inreg %x) nounwind {
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; X86-64: movl %edi, %eax
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; X86-64: movzbl %ah, %eax
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; WIN64: qux16:
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; WIN64: movzbl %ch, %eax
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; X86-32: qux16:
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; X86-32: movzbl %ah, %eax
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%t0 = lshr i16 %x, 8
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@ -1,4 +1,9 @@
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; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | grep {pshufd \$3, %xmm0, %xmm0}
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2,-sse41 | FileCheck %s
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; CHECK: pshufd $3, %xmm0, %xmm0
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; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2,-sse41 | FileCheck %s -check-prefix=WIN64
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; %a is passed indirectly on Win64.
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; WIN64: movss 12(%rcx), %xmm0
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define float @foo(<8 x float> %a) nounwind {
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%c = extractelement <8 x float> %a, i32 3
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@ -1,8 +1,13 @@
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; RUN: llc < %s -march=x86-64 -mattr=+sse41 -asm-verbose=0 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse41 -asm-verbose=0 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse41 -asm-verbose=0 | FileCheck %s -check-prefix=WIN64
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define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
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; CHECK: test1:
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; CHECK-NEXT: pmulld
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; WIN64: test1:
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; WIN64-NEXT: movdqa (%rcx), %xmm0
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; WIN64-NEXT: pmulld (%rdx), %xmm0
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%C = mul <4 x i32> %A, %B
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ret <4 x i32> %C
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}
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@ -10,6 +15,11 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
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define <4 x i32> @test1a(<4 x i32> %A, <4 x i32> *%Bp) nounwind {
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; CHECK: test1a:
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; CHECK-NEXT: pmulld
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; WIN64: test1a:
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; WIN64-NEXT: movdqa (%rcx), %xmm0
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; WIN64-NEXT: pmulld (%rdx), %xmm0
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%B = load <4 x i32>* %Bp
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%C = mul <4 x i32> %A, %B
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ret <4 x i32> %C
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@ -1,4 +1,5 @@
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; RUN: llc < %s -march=x86-64 -mcpu=penryn -asm-verbose=0 -o - | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-linux -mcpu=penryn -asm-verbose=0 -o - | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=penryn -asm-verbose=0 -o - | FileCheck %s -check-prefix=W64
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; RUN: llc < %s -mcpu=yonah -march=x86 -asm-verbose=0 -o - | FileCheck %s -check-prefix=X32
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; PR7518
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@ -15,6 +16,13 @@ define void @test1(<2 x float> %Q, float *%P2) nounwind {
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; X64-NEXT: movss %xmm1, (%rdi)
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; X64-NEXT: ret
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; W64: test1:
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; W64-NEXT: movdqa (%rcx), %xmm0
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; W64-NEXT: pshufd $1, %xmm0, %xmm1
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; W64-NEXT: addss %xmm0, %xmm1
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; W64-NEXT: movss %xmm1, (%rdx)
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; W64-NEXT: ret
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; X32: test1:
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; X32-NEXT: pshufd $1, %xmm0, %xmm1
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; X32-NEXT: addss %xmm0, %xmm1
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@ -31,6 +39,14 @@ define <2 x float> @test2(<2 x float> %Q, <2 x float> %R, <2 x float> *%P) nounw
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; X64: test2:
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; X64-NEXT: addps %xmm1, %xmm0
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; X64-NEXT: ret
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; W64: test2:
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; W64-NEXT: movaps (%rcx), %xmm0
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; W64-NEXT: addps (%rdx), %xmm0
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; W64-NEXT: ret
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; X32: test2:
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; X32: addps %xmm1, %xmm0
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}
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@ -38,17 +54,35 @@ define <2 x float> @test3(<4 x float> %A) nounwind {
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%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
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%C = fadd <2 x float> %B, %B
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ret <2 x float> %C
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; CHECK: test3:
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; CHECK-NEXT: addps %xmm0, %xmm0
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; CHECK-NEXT: ret
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; X64: test3:
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; X64-NEXT: addps %xmm0, %xmm0
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; X64-NEXT: ret
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; W64: test3:
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; W64-NEXT: movaps (%rcx), %xmm0
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; W64-NEXT: addps %xmm0, %xmm0
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; W64-NEXT: ret
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; X32: test3:
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; X32-NEXT: addps %xmm0, %xmm0
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; X32-NEXT: ret
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}
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define <2 x float> @test4(<2 x float> %A) nounwind {
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%C = fadd <2 x float> %A, %A
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ret <2 x float> %C
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; CHECK: test4:
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; CHECK-NEXT: addps %xmm0, %xmm0
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; CHECK-NEXT: ret
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; X64: test4:
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; X64-NEXT: addps %xmm0, %xmm0
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; X64-NEXT: ret
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; W64: test4:
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; W64-NEXT: movaps (%rcx), %xmm0
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; W64-NEXT: addps %xmm0, %xmm0
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; W64-NEXT: ret
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; X32: test4:
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; X32-NEXT: addps %xmm0, %xmm0
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; X32-NEXT: ret
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}
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define <4 x float> @test5(<4 x float> %A) nounwind {
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@ -61,10 +95,21 @@ BB:
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%E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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ret <4 x float> %E
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; CHECK: _test5:
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; CHECK-NEXT: addps %xmm0, %xmm0
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; CHECK-NEXT: addps %xmm0, %xmm0
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; CHECK-NEXT: ret
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; X64: test5:
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; X64-NEXT: addps %xmm0, %xmm0
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; X64-NEXT: addps %xmm0, %xmm0
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; X64-NEXT: ret
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; W64: test5:
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; W64-NEXT: movaps (%rcx), %xmm0
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; W64-NEXT: addps %xmm0, %xmm0
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; W64-NEXT: addps %xmm0, %xmm0
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; W64-NEXT: ret
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; X32: test5:
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; X32-NEXT: addps %xmm0, %xmm0
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; X32-NEXT: addps %xmm0, %xmm0
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; X32-NEXT: ret
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}
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@ -1,4 +1,5 @@
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; RUN: llc < %s -o - -march=x86-64 | FileCheck %s
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; RUN: llc < %s -o - -mtriple=x86_64-linux | FileCheck %s
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; RUN: llc < %s -o - -mtriple=x86_64-win32 | FileCheck %s -check-prefix=WIN64
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; PR4891
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; Both loads should happen before either store.
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@ -8,6 +9,11 @@
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; CHECK: movl %ecx, (%rdi)
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; CHECK: movl %eax, (%rsi)
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; WIN64: movl (%rcx), %eax
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; WIN64: movl (%rdx), %esi
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; WIN64: movl %esi, (%rcx)
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; WIN64: movl %eax, (%rdx)
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define void @short2_int_swap(<2 x i16>* nocapture %b, i32* nocapture %c) nounwind {
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entry:
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%0 = load <2 x i16>* %b, align 2 ; <<2 x i16>> [#uses=1]
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