RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-24 20:29:53 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

PR19320:

Browse Source 
The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP.
It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stepan Dyatkovskiy 2014-04-03 11:29:15 +00:00
parent 3f11cd0d25
commit 37e5cfa4aa
2 changed files with 18 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5408,11 +5408,16 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
Operands.size() == 4) {
ARMOperand *Op = static_cast<ARMOperand *>(Operands[2]);
assert(Op->isReg() && "expected register argument");
assert(MRI->getMatchingSuperReg(Op->getReg(), ARM::gsub_0,
&MRI->getRegClass(ARM::GPRPairRegClassID))
&& "expected register pair");
unsigned SuperReg = MRI->getMatchingSuperReg(
Op->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
assert(SuperReg && "expected register pair");
unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
Operands.insert(Operands.begin() + 3,
ARMOperand::CreateReg(Op->getReg() + 1, Op->getStartLoc(),
ARMOperand::CreateReg(PairedReg, Op->getStartLoc(),
Op->getEndLoc()));
}

9
test/MC/ARM/ldrd-strd-gnu-sp.s Normal file
View File

@ -0,0 +1,9 @@
// PR19320
// RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
.text
// CHECK: ldrd r12, sp, [r0, #32] @ encoding: [0xd0,0xc2,0xc0,0xe1]
ldrd r12, [r0, #32]
// CHECK: strd r12, sp, [r0, #32] @ encoding: [0xf0,0xc2,0xc0,0xe1]
strd r12, [r0, #32]