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Refactor ARM instruction format definitions into a separate file. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55518 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
99b218218c
commit
37f25d989a
228
lib/Target/ARM/ARMInstrFormats.td
Normal file
228
lib/Target/ARM/ARMInstrFormats.td
Normal file
@ -0,0 +1,228 @@
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//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// ARM Instruction Format Definitions.
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//
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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class Format<bits<5> val> {
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bits<5> Value = val;
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}
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def Pseudo : Format<1>;
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def MulFrm : Format<2>;
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def MulSMLAW : Format<3>;
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def MulSMULW : Format<4>;
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def MulSMLA : Format<5>;
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def MulSMUL : Format<6>;
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def Branch : Format<7>;
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def BranchMisc : Format<8>;
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def DPRdIm : Format<9>;
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def DPRdReg : Format<10>;
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def DPRdSoReg : Format<11>;
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def DPRdMisc : Format<12>;
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def DPRnIm : Format<13>;
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def DPRnReg : Format<14>;
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def DPRnSoReg : Format<15>;
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def DPRIm : Format<16>;
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def DPRReg : Format<17>;
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def DPRSoReg : Format<18>;
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def DPRImS : Format<19>;
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def DPRRegS : Format<20>;
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def DPRSoRegS : Format<21>;
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def LdFrm : Format<22>;
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def StFrm : Format<23>;
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def ArithMisc : Format<24>;
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def ThumbFrm : Format<25>;
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def VFPFrm : Format<26>;
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//===----------------------------------------------------------------------===//
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// ARM Instruction templates.
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//
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class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
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Format f, string cstr>
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: Instruction {
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let Namespace = "ARM";
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bits<4> Opcode = opcod;
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AddrMode AM = am;
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bits<4> AddrModeBits = AM.Value;
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SizeFlagVal SZ = sz;
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bits<3> SizeFlag = SZ.Value;
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IndexMode IM = im;
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bits<2> IndexModeBits = IM.Value;
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Format F = f;
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bits<5> Form = F.Value;
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let Constraints = cstr;
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}
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class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
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: InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
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let OutOperandList = oops;
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let InOperandList = iops;
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let AsmString = asm;
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let Pattern = pattern;
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}
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// Almost all ARM instructions are predicable.
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class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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IndexMode im, Format f, string opc, string asm, string cstr,
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list<dag> pattern>
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: InstARM<opcod, am, sz, im, f, cstr> {
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let OutOperandList = oops;
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let InOperandList = !con(iops, (ops pred:$p));
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let AsmString = !strconcat(opc, !strconcat("${p}", asm));
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let Pattern = pattern;
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list<Predicate> Predicates = [IsARM];
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}
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// Same as I except it can optionally modify CPSR. Note it's modeled as
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// an input operand since by default it's a zero register. It will
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// become an implicit def once it's "flipped".
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class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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IndexMode im, Format f, string opc, string asm, string cstr,
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list<dag> pattern>
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: InstARM<opcod, am, sz, im, f, cstr> {
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let OutOperandList = oops;
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let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
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let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
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let Pattern = pattern;
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list<Predicate> Predicates = [IsARM];
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}
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class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
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asm,"",pattern>;
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class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
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asm,"",pattern>;
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class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern>;
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class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern>;
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class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern>;
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class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern>;
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class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern>;
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class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
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asm, "", pattern>;
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// Pre-indexed ops
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class AI2pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
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asm, cstr, pattern>;
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class AI3pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
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asm, cstr, pattern>;
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// Post-indexed ops
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class AI2po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
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asm, cstr,pattern>;
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class AI3po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
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asm, cstr,pattern>;
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// Special cases.
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class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
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: InstARM<opcod, am, sz, im, f, cstr> {
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let OutOperandList = oops;
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let InOperandList = iops;
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let AsmString = asm;
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let Pattern = pattern;
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list<Predicate> Predicates = [IsARM];
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}
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class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
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"", pattern>;
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class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
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"", pattern>;
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class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
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"", pattern>;
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class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
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"", pattern>;
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class AXI4<bits<4> opcod, dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
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"", pattern>;
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class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
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list<dag> pattern>
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: XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
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"", pattern>;
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// BR_JT instructions
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class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
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: XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
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asm, "", pattern>;
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class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
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: XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
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asm, "", pattern>;
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class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
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: XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
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asm, "", pattern>;
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//===----------------------------------------------------------------------===//
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// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
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class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsARM];
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}
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class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsARM, HasV5TE];
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}
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class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsARM, HasV6];
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}
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@ -155,7 +155,8 @@ def sext_16_node : PatLeaf<(i32 GPR:$a), [{
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return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
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}]>;
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class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
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class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
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//===----------------------------------------------------------------------===//
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// Operand Definitions.
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@ -330,177 +331,13 @@ def IndexModePre : IndexMode<1>;
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def IndexModePost : IndexMode<2>;
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//===----------------------------------------------------------------------===//
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// ARM Instruction Format Definitions.
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//
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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class Format<bits<5> val> {
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bits<5> Value = val;
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}
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def Pseudo : Format<1>;
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def MulFrm : Format<2>;
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def MulSMLAW : Format<3>;
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def MulSMULW : Format<4>;
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def MulSMLA : Format<5>;
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def MulSMUL : Format<6>;
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def Branch : Format<7>;
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def BranchMisc : Format<8>;
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def DPRdIm : Format<9>;
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def DPRdReg : Format<10>;
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def DPRdSoReg : Format<11>;
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def DPRdMisc : Format<12>;
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def DPRnIm : Format<13>;
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def DPRnReg : Format<14>;
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def DPRnSoReg : Format<15>;
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def DPRIm : Format<16>;
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def DPRReg : Format<17>;
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def DPRSoReg : Format<18>;
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def DPRImS : Format<19>;
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def DPRRegS : Format<20>;
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def DPRSoRegS : Format<21>;
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def LdFrm : Format<22>;
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def StFrm : Format<23>;
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def ArithMisc : Format<24>;
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def ThumbFrm : Format<25>;
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def VFPFrm : Format<26>;
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include "ARMInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// ARM Instruction templates.
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// Multiclass helpers...
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//
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// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
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class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsARM];
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}
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class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsARM, HasV5TE];
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}
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class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsARM, HasV6];
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}
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class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
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Format f, string cstr>
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: Instruction {
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let Namespace = "ARM";
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bits<4> Opcode = opcod;
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AddrMode AM = am;
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bits<4> AddrModeBits = AM.Value;
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SizeFlagVal SZ = sz;
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bits<3> SizeFlag = SZ.Value;
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IndexMode IM = im;
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bits<2> IndexModeBits = IM.Value;
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Format F = f;
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bits<5> Form = F.Value;
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let Constraints = cstr;
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}
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class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
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: InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
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let OutOperandList = oops;
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let InOperandList = iops;
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let AsmString = asm;
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let Pattern = pattern;
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}
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// Almost all ARM instructions are predicable.
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class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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IndexMode im, Format f, string opc, string asm, string cstr,
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list<dag> pattern>
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: InstARM<opcod, am, sz, im, f, cstr> {
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let OutOperandList = oops;
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let InOperandList = !con(iops, (ops pred:$p));
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let AsmString = !strconcat(opc, !strconcat("${p}", asm));
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let Pattern = pattern;
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list<Predicate> Predicates = [IsARM];
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}
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// Same as I except it can optionally modify CPSR. Note it's modeled as
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// an input operand since by default it's a zero register. It will
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// become an implicit def once it's "flipped".
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class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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IndexMode im, Format f, string opc, string asm, string cstr,
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list<dag> pattern>
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: InstARM<opcod, am, sz, im, f, cstr> {
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let OutOperandList = oops;
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let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
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let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
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let Pattern = pattern;
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list<Predicate> Predicates = [IsARM];
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}
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class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
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asm,"",pattern>;
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class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
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asm,"",pattern>;
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class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern>;
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class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern>;
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class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern>;
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class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern>;
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class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
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asm, "", pattern>;
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class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
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asm, "", pattern>;
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// Pre-indexed ops
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class AI2pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
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asm, cstr, pattern>;
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class AI3pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
string asm, string cstr, list<dag> pattern>
|
||||
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
|
||||
asm, cstr, pattern>;
|
||||
|
||||
// Post-indexed ops
|
||||
class AI2po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
string asm, string cstr, list<dag> pattern>
|
||||
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
|
||||
asm, cstr,pattern>;
|
||||
class AI3po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
|
||||
string asm, string cstr, list<dag> pattern>
|
||||
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
|
||||
asm, cstr,pattern>;
|
||||
|
||||
|
||||
class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
|
||||
class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
|
||||
|
||||
|
||||
/// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
|
||||
/// binop that produces a value.
|
||||
multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
|
||||
@ -574,54 +411,6 @@ multiclass AI_bin_rrot<bits<4> opcod, string opc, PatFrag opnode> {
|
||||
Requires<[IsARM, HasV6]>;
|
||||
}
|
||||
|
||||
// Special cases.
|
||||
class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
|
||||
IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
|
||||
: InstARM<opcod, am, sz, im, f, cstr> {
|
||||
let OutOperandList = oops;
|
||||
let InOperandList = iops;
|
||||
let AsmString = asm;
|
||||
let Pattern = pattern;
|
||||
list<Predicate> Predicates = [IsARM];
|
||||
}
|
||||
|
||||
class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
|
||||
list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
|
||||
"", pattern>;
|
||||
class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
|
||||
list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
|
||||
"", pattern>;
|
||||
class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
|
||||
list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
|
||||
"", pattern>;
|
||||
class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
|
||||
list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
|
||||
"", pattern>;
|
||||
class AXI4<bits<4> opcod, dag oops, dag iops, Format f, string asm,
|
||||
list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
|
||||
"", pattern>;
|
||||
|
||||
class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
|
||||
list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
|
||||
"", pattern>;
|
||||
|
||||
// BR_JT instructions
|
||||
class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
|
||||
asm, "", pattern>;
|
||||
class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
|
||||
asm, "", pattern>;
|
||||
class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
|
||||
: XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
|
||||
asm, "", pattern>;
|
||||
|
||||
/// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
|
||||
/// setting carry bit. But it can optionally set CPSR.
|
||||
let Uses = [CPSR] in {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user