From 37f25d989a3054b4742f6c92af94a312c26ffb2b Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 28 Aug 2008 23:39:26 +0000 Subject: [PATCH] Refactor ARM instruction format definitions into a separate file. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55518 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrFormats.td | 228 ++++++++++++++++++++++++++++++ lib/Target/ARM/ARMInstrInfo.td | 219 +--------------------------- 2 files changed, 232 insertions(+), 215 deletions(-) create mode 100644 lib/Target/ARM/ARMInstrFormats.td diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td new file mode 100644 index 00000000000..b1a7715db98 --- /dev/null +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -0,0 +1,228 @@ +//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// +// ARM Instruction Format Definitions. +// + +// Format specifies the encoding used by the instruction. This is part of the +// ad-hoc solution used to emit machine instruction encodings by our machine +// code emitter. +class Format val> { + bits<5> Value = val; +} + +def Pseudo : Format<1>; +def MulFrm : Format<2>; +def MulSMLAW : Format<3>; +def MulSMULW : Format<4>; +def MulSMLA : Format<5>; +def MulSMUL : Format<6>; +def Branch : Format<7>; +def BranchMisc : Format<8>; + +def DPRdIm : Format<9>; +def DPRdReg : Format<10>; +def DPRdSoReg : Format<11>; +def DPRdMisc : Format<12>; +def DPRnIm : Format<13>; +def DPRnReg : Format<14>; +def DPRnSoReg : Format<15>; +def DPRIm : Format<16>; +def DPRReg : Format<17>; +def DPRSoReg : Format<18>; +def DPRImS : Format<19>; +def DPRRegS : Format<20>; +def DPRSoRegS : Format<21>; + +def LdFrm : Format<22>; +def StFrm : Format<23>; + +def ArithMisc : Format<24>; +def ThumbFrm : Format<25>; +def VFPFrm : Format<26>; + + + +//===----------------------------------------------------------------------===// + +// ARM Instruction templates. +// + +class InstARM opcod, AddrMode am, SizeFlagVal sz, IndexMode im, + Format f, string cstr> + : Instruction { + let Namespace = "ARM"; + + bits<4> Opcode = opcod; + AddrMode AM = am; + bits<4> AddrModeBits = AM.Value; + + SizeFlagVal SZ = sz; + bits<3> SizeFlag = SZ.Value; + + IndexMode IM = im; + bits<2> IndexModeBits = IM.Value; + + Format F = f; + bits<5> Form = F.Value; + + let Constraints = cstr; +} + +class PseudoInst pattern> + : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> { + let OutOperandList = oops; + let InOperandList = iops; + let AsmString = asm; + let Pattern = pattern; +} + +// Almost all ARM instructions are predicable. +class I opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, + IndexMode im, Format f, string opc, string asm, string cstr, + list pattern> + : InstARM { + let OutOperandList = oops; + let InOperandList = !con(iops, (ops pred:$p)); + let AsmString = !strconcat(opc, !strconcat("${p}", asm)); + let Pattern = pattern; + list Predicates = [IsARM]; +} + +// Same as I except it can optionally modify CPSR. Note it's modeled as +// an input operand since by default it's a zero register. It will +// become an implicit def once it's "flipped". +class sI opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, + IndexMode im, Format f, string opc, string asm, string cstr, + list pattern> + : InstARM { + let OutOperandList = oops; + let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); + let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); + let Pattern = pattern; + list Predicates = [IsARM]; +} + +class AI opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : I; +class AsI opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : sI; +class AI1 opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : I; +class AsI1 opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : sI; +class AI2 opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : I; +class AI3 opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : I; +class AI4 opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : I; +class AI1x2 opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : I; + +// Pre-indexed ops +class AI2pr opcod, dag oops, dag iops, Format f, string opc, + string asm, string cstr, list pattern> + : I; +class AI3pr opcod, dag oops, dag iops, Format f, string opc, + string asm, string cstr, list pattern> + : I; + +// Post-indexed ops +class AI2po opcod, dag oops, dag iops, Format f, string opc, + string asm, string cstr, list pattern> + : I; +class AI3po opcod, dag oops, dag iops, Format f, string opc, + string asm, string cstr, list pattern> + : I; + + +// Special cases. +class XI opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, + IndexMode im, Format f, string asm, string cstr, list pattern> + : InstARM { + let OutOperandList = oops; + let InOperandList = iops; + let AsmString = asm; + let Pattern = pattern; + list Predicates = [IsARM]; +} + +class AXI opcod, dag oops, dag iops, Format f, string asm, + list pattern> + : XI; +class AXI1 opcod, dag oops, dag iops, Format f, string asm, + list pattern> + : XI; +class AXI2 opcod, dag oops, dag iops, Format f, string asm, + list pattern> + : XI; +class AXI3 opcod, dag oops, dag iops, Format f, string asm, + list pattern> + : XI; +class AXI4 opcod, dag oops, dag iops, Format f, string asm, + list pattern> + : XI; + +class AXIx2 opcod, dag oops, dag iops, Format f, string asm, + list pattern> + : XI; + +// BR_JT instructions +class JTI opcod, dag oops, dag iops, string asm, list pattern> + : XI; +class JTI1 opcod, dag oops, dag iops, string asm, list pattern> + : XI; +class JTI2 opcod, dag oops, dag iops, string asm, list pattern> + : XI; + + +//===----------------------------------------------------------------------===// + +// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. +class ARMPat : Pat { + list Predicates = [IsARM]; +} +class ARMV5TEPat : Pat { + list Predicates = [IsARM, HasV5TE]; +} +class ARMV6Pat : Pat { + list Predicates = [IsARM, HasV6]; +} diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index a5719e4f131..c91ac396c6c 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -155,7 +155,8 @@ def sext_16_node : PatLeaf<(i32 GPR:$a), [{ return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; }]>; - +class BinOpFrag : PatFrag<(ops node:$LHS, node:$RHS), res>; +class UnOpFrag : PatFrag<(ops node:$Src), res>; //===----------------------------------------------------------------------===// // Operand Definitions. @@ -330,177 +331,13 @@ def IndexModePre : IndexMode<1>; def IndexModePost : IndexMode<2>; //===----------------------------------------------------------------------===// -// ARM Instruction Format Definitions. -// - -// Format specifies the encoding used by the instruction. This is part of the -// ad-hoc solution used to emit machine instruction encodings by our machine -// code emitter. -class Format val> { - bits<5> Value = val; -} - -def Pseudo : Format<1>; -def MulFrm : Format<2>; -def MulSMLAW : Format<3>; -def MulSMULW : Format<4>; -def MulSMLA : Format<5>; -def MulSMUL : Format<6>; -def Branch : Format<7>; -def BranchMisc : Format<8>; - -def DPRdIm : Format<9>; -def DPRdReg : Format<10>; -def DPRdSoReg : Format<11>; -def DPRdMisc : Format<12>; -def DPRnIm : Format<13>; -def DPRnReg : Format<14>; -def DPRnSoReg : Format<15>; -def DPRIm : Format<16>; -def DPRReg : Format<17>; -def DPRSoReg : Format<18>; -def DPRImS : Format<19>; -def DPRRegS : Format<20>; -def DPRSoRegS : Format<21>; - -def LdFrm : Format<22>; -def StFrm : Format<23>; - -def ArithMisc : Format<24>; -def ThumbFrm : Format<25>; -def VFPFrm : Format<26>; - +include "ARMInstrFormats.td" //===----------------------------------------------------------------------===// - -// ARM Instruction templates. +// Multiclass helpers... // -// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. -class ARMPat : Pat { - list Predicates = [IsARM]; -} -class ARMV5TEPat : Pat { - list Predicates = [IsARM, HasV5TE]; -} -class ARMV6Pat : Pat { - list Predicates = [IsARM, HasV6]; -} - -class InstARM opcod, AddrMode am, SizeFlagVal sz, IndexMode im, - Format f, string cstr> - : Instruction { - let Namespace = "ARM"; - - bits<4> Opcode = opcod; - AddrMode AM = am; - bits<4> AddrModeBits = AM.Value; - - SizeFlagVal SZ = sz; - bits<3> SizeFlag = SZ.Value; - - IndexMode IM = im; - bits<2> IndexModeBits = IM.Value; - - Format F = f; - bits<5> Form = F.Value; - - let Constraints = cstr; -} - -class PseudoInst pattern> - : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> { - let OutOperandList = oops; - let InOperandList = iops; - let AsmString = asm; - let Pattern = pattern; -} - -// Almost all ARM instructions are predicable. -class I opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, - IndexMode im, Format f, string opc, string asm, string cstr, - list pattern> - : InstARM { - let OutOperandList = oops; - let InOperandList = !con(iops, (ops pred:$p)); - let AsmString = !strconcat(opc, !strconcat("${p}", asm)); - let Pattern = pattern; - list Predicates = [IsARM]; -} - -// Same as I except it can optionally modify CPSR. Note it's modeled as -// an input operand since by default it's a zero register. It will -// become an implicit def once it's "flipped". -class sI opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, - IndexMode im, Format f, string opc, string asm, string cstr, - list pattern> - : InstARM { - let OutOperandList = oops; - let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); - let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); - let Pattern = pattern; - list Predicates = [IsARM]; -} - -class AI opcod, dag oops, dag iops, Format f, string opc, - string asm, list pattern> - : I; -class AsI opcod, dag oops, dag iops, Format f, string opc, - string asm, list pattern> - : sI; -class AI1 opcod, dag oops, dag iops, Format f, string opc, - string asm, list pattern> - : I; -class AsI1 opcod, dag oops, dag iops, Format f, string opc, - string asm, list pattern> - : sI; -class AI2 opcod, dag oops, dag iops, Format f, string opc, - string asm, list pattern> - : I; -class AI3 opcod, dag oops, dag iops, Format f, string opc, - string asm, list pattern> - : I; -class AI4 opcod, dag oops, dag iops, Format f, string opc, - string asm, list pattern> - : I; -class AI1x2 opcod, dag oops, dag iops, Format f, string opc, - string asm, list pattern> - : I; - -// Pre-indexed ops -class AI2pr opcod, dag oops, dag iops, Format f, string opc, - string asm, string cstr, list pattern> - : I; -class AI3pr opcod, dag oops, dag iops, Format f, string opc, - string asm, string cstr, list pattern> - : I; - -// Post-indexed ops -class AI2po opcod, dag oops, dag iops, Format f, string opc, - string asm, string cstr, list pattern> - : I; -class AI3po opcod, dag oops, dag iops, Format f, string opc, - string asm, string cstr, list pattern> - : I; - - -class BinOpFrag : PatFrag<(ops node:$LHS, node:$RHS), res>; -class UnOpFrag : PatFrag<(ops node:$Src), res>; - - /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a /// binop that produces a value. multiclass AsI1_bin_irs opcod, string opc, PatFrag opnode> { @@ -574,54 +411,6 @@ multiclass AI_bin_rrot opcod, string opc, PatFrag opnode> { Requires<[IsARM, HasV6]>; } -// Special cases. -class XI opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, - IndexMode im, Format f, string asm, string cstr, list pattern> - : InstARM { - let OutOperandList = oops; - let InOperandList = iops; - let AsmString = asm; - let Pattern = pattern; - list Predicates = [IsARM]; -} - -class AXI opcod, dag oops, dag iops, Format f, string asm, - list pattern> - : XI; -class AXI1 opcod, dag oops, dag iops, Format f, string asm, - list pattern> - : XI; -class AXI2 opcod, dag oops, dag iops, Format f, string asm, - list pattern> - : XI; -class AXI3 opcod, dag oops, dag iops, Format f, string asm, - list pattern> - : XI; -class AXI4 opcod, dag oops, dag iops, Format f, string asm, - list pattern> - : XI; - -class AXIx2 opcod, dag oops, dag iops, Format f, string asm, - list pattern> - : XI; - -// BR_JT instructions -class JTI opcod, dag oops, dag iops, string asm, list pattern> - : XI; -class JTI1 opcod, dag oops, dag iops, string asm, list pattern> - : XI; -class JTI2 opcod, dag oops, dag iops, string asm, list pattern> - : XI; - /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and /// setting carry bit. But it can optionally set CPSR. let Uses = [CPSR] in {