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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122368 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
parent
c72b18cdc8
commit
38036d8b36
@ -193,7 +193,7 @@ void ScheduleDAGRRList::Schedule() {
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<< " '" << BB->getName() << "' **********\n");
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NumLiveRegs = 0;
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LiveRegDefs.resize(TRI->getNumRegs(), NULL);
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LiveRegDefs.resize(TRI->getNumRegs(), NULL);
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LiveRegCycles.resize(TRI->getNumRegs(), 0);
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// Build the scheduling graph.
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@ -204,13 +204,13 @@ void ScheduleDAGRRList::Schedule() {
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Topo.InitDAGTopologicalSorting();
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AvailableQueue->initNodes(SUnits);
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// Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
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if (isBottomUp)
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ListScheduleBottomUp();
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else
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ListScheduleTopDown();
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AvailableQueue->releaseState();
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}
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@ -254,7 +254,7 @@ void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU, unsigned CurCycle) {
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ReleasePred(SU, &*I);
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if (I->isAssignedRegDep()) {
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// This is a physical register dependency and it's impossible or
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// expensive to copy the register. Make sure nothing that can
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// expensive to copy the register. Make sure nothing that can
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// clobber the register is scheduled between the predecessor and
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// this node.
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if (!LiveRegDefs[I->getReg()]) {
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@ -307,7 +307,7 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
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/// CapturePred - This does the opposite of ReleasePred. Since SU is being
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/// unscheduled, incrcease the succ left count of its predecessors. Remove
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/// them from AvailableQueue if necessary.
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void ScheduleDAGRRList::CapturePred(SDep *PredEdge) {
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void ScheduleDAGRRList::CapturePred(SDep *PredEdge) {
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SUnit *PredSU = PredEdge->getSUnit();
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if (PredSU->isAvailable) {
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PredSU->isAvailable = false;
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@ -447,7 +447,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
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SUnit *NewSU = CreateNewSUnit(N);
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NewSU->NodeNum);
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const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
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for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
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if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
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@ -517,7 +517,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
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D.setSUnit(LoadSU);
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AddPred(SuccDep, D);
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}
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}
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}
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// Add a data dependency to reflect that NewSU reads the value defined
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// by LoadSU.
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@ -702,21 +702,21 @@ DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) {
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for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg)
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CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
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}
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// Okay, we now know all of the live registers that are defined by an
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// immediate predecessor. It is ok to kill these registers if we are also
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// using it.
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->isAssignedRegDep() &&
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if (I->isAssignedRegDep() &&
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LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) {
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unsigned Reg = I->getReg();
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if (RegAdded.erase(Reg))
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LRegs.erase(std::find(LRegs.begin(), LRegs.end(), Reg));
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}
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}
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return !LRegs.empty();
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}
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@ -867,7 +867,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
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// Reverse the order if it is bottom up.
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std::reverse(Sequence.begin(), Sequence.end());
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#ifndef NDEBUG
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VerifySchedule(isBottomUp);
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#endif
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@ -944,19 +944,19 @@ void ScheduleDAGRRList::ListScheduleTopDown() {
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SUnits[i].isAvailable = true;
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}
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}
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// While Available queue is not empty, grab the node with the highest
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// priority. If it is not ready put it back. Schedule the node.
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Sequence.reserve(SUnits.size());
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while (!AvailableQueue->empty()) {
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SUnit *CurSU = AvailableQueue->pop();
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if (CurSU)
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ScheduleNodeTopDown(CurSU, CurCycle);
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++CurCycle;
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AvailableQueue->setCurCycle(CurCycle);
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}
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#ifndef NDEBUG
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VerifySchedule(isBottomUp);
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#endif
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@ -969,18 +969,18 @@ void ScheduleDAGRRList::ListScheduleTopDown() {
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//
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// This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
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// to reduce register pressure.
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//
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//
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namespace {
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template<class SF>
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class RegReductionPriorityQueue;
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/// bu_ls_rr_sort - Priority function for bottom up register pressure
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// reduction scheduler.
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struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
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RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ;
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bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {}
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bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
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bool operator()(const SUnit* left, const SUnit* right) const;
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};
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@ -990,7 +990,7 @@ namespace {
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RegReductionPriorityQueue<td_ls_rr_sort> *SPQ;
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td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {}
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td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
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bool operator()(const SUnit* left, const SUnit* right) const;
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};
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@ -1001,7 +1001,7 @@ namespace {
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: SPQ(spq) {}
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src_ls_rr_sort(const src_ls_rr_sort &RHS)
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: SPQ(RHS.SPQ) {}
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bool operator()(const SUnit* left, const SUnit* right) const;
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};
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@ -1054,7 +1054,7 @@ CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
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if (SethiUllmanNumber == 0)
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SethiUllmanNumber = 1;
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return SethiUllmanNumber;
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}
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@ -1106,7 +1106,7 @@ namespace {
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RegLimit[(*I)->getID()] = tli->getRegPressureLimit(*I, MF);
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}
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}
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void initNodes(std::vector<SUnit> &sunits) {
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SUnits = &sunits;
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// Add pseudo dependency edges for two-address nodes.
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@ -1167,7 +1167,7 @@ namespace {
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}
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bool empty() const { return Queue.empty(); }
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void push(SUnit *U) {
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assert(!U->NodeQueueId && "Node in the queue already");
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U->NodeQueueId = ++CurQueueId;
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@ -1231,7 +1231,7 @@ namespace {
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// class to the point where it would cause spills.
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if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
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return true;
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continue;
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continue;
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} else if (POpc == TargetOpcode::INSERT_SUBREG ||
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POpc == TargetOpcode::SUBREG_TO_REG) {
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EVT VT = PN->getValueType(0);
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@ -1303,7 +1303,7 @@ namespace {
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EVT VT = PN->getOperand(0).getValueType();
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
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continue;
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continue;
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} else if (POpc == TargetOpcode::INSERT_SUBREG ||
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POpc == TargetOpcode::SUBREG_TO_REG) {
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EVT VT = PN->getValueType(0);
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@ -1382,7 +1382,7 @@ namespace {
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EVT VT = PN->getOperand(0).getValueType();
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
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continue;
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continue;
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} else if (POpc == TargetOpcode::INSERT_SUBREG ||
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POpc == TargetOpcode::SUBREG_TO_REG) {
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EVT VT = PN->getValueType(0);
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@ -1422,8 +1422,8 @@ namespace {
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dumpRegPressure();
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}
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void setScheduleDAG(ScheduleDAGRRList *scheduleDag) {
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scheduleDAG = scheduleDag;
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void setScheduleDAG(ScheduleDAGRRList *scheduleDag) {
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scheduleDAG = scheduleDag;
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}
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void dumpRegPressure() const {
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@ -1570,11 +1570,11 @@ static bool BURRSort(const SUnit *left, const SUnit *right,
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if (left->getHeight() != right->getHeight())
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return left->getHeight() > right->getHeight();
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if (left->getDepth() != right->getDepth())
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return left->getDepth() < right->getDepth();
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assert(left->NodeQueueId && right->NodeQueueId &&
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assert(left->NodeQueueId && right->NodeQueueId &&
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"NodeQueueId cannot be zero");
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return (left->NodeQueueId > right->NodeQueueId);
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}
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@ -1944,7 +1944,7 @@ void RegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
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template<class SF>
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void RegReductionPriorityQueue<SF>::CalculateSethiUllmanNumbers() {
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SethiUllmanNumbers.assign(SUnits->size(), 0);
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for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
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CalcNodeSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers);
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}
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@ -1952,7 +1952,7 @@ void RegReductionPriorityQueue<SF>::CalculateSethiUllmanNumbers() {
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/// LimitedSumOfUnscheduledPredsOfSuccs - Compute the sum of the unscheduled
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/// predecessors of the successors of the SUnit SU. Stop when the provided
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/// limit is exceeded.
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static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU,
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static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU,
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unsigned Limit) {
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unsigned Sum = 0;
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for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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@ -2004,7 +2004,7 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
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if (left->NumSuccsLeft != right->NumSuccsLeft)
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return left->NumSuccsLeft > right->NumSuccsLeft;
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assert(left->NodeQueueId && right->NodeQueueId &&
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assert(left->NodeQueueId && right->NodeQueueId &&
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"NodeQueueId cannot be zero");
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return (left->NodeQueueId > right->NodeQueueId);
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}
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@ -2018,12 +2018,12 @@ llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
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const TargetMachine &TM = IS->TM;
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const TargetInstrInfo *TII = TM.getInstrInfo();
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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BURegReductionPriorityQueue *PQ =
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new BURegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
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ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
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PQ->setScheduleDAG(SD);
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return SD;
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return SD;
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}
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llvm::ScheduleDAGSDNodes *
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@ -2031,7 +2031,7 @@ llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
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const TargetMachine &TM = IS->TM;
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const TargetInstrInfo *TII = TM.getInstrInfo();
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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TDRegReductionPriorityQueue *PQ =
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new TDRegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
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ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, false, PQ);
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@ -2044,12 +2044,12 @@ llvm::createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
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const TargetMachine &TM = IS->TM;
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const TargetInstrInfo *TII = TM.getInstrInfo();
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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SrcRegReductionPriorityQueue *PQ =
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new SrcRegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
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ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
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PQ->setScheduleDAG(SD);
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return SD;
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return SD;
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}
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llvm::ScheduleDAGSDNodes *
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@ -2058,12 +2058,12 @@ llvm::createHybridListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
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const TargetInstrInfo *TII = TM.getInstrInfo();
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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const TargetLowering *TLI = &IS->getTargetLowering();
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HybridBURRPriorityQueue *PQ =
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new HybridBURRPriorityQueue(*IS->MF, true, TII, TRI, TLI);
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ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, true, PQ);
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PQ->setScheduleDAG(SD);
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return SD;
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return SD;
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}
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llvm::ScheduleDAGSDNodes *
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@ -2072,10 +2072,10 @@ llvm::createILPListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
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const TargetInstrInfo *TII = TM.getInstrInfo();
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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const TargetLowering *TLI = &IS->getTargetLowering();
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ILPBURRPriorityQueue *PQ =
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new ILPBURRPriorityQueue(*IS->MF, true, TII, TRI, TLI);
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ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, true, PQ);
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PQ->setScheduleDAG(SD);
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return SD;
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return SD;
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}
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