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fix some obvious typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83768 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -650,7 +650,7 @@ it run faster:</p>
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from the compiler. It works well for many simple C testcases, but doesn't
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support exception handling, debug info, inline assembly, etc.</li>
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<li>Targets can now specify register allocation hints through
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MachineRegisterInfo:: setRegAllocationHint. A regalloc hint consists of hint
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MachineRegisterInfo::setRegAllocationHint. A regalloc hint consists of hint
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type and physical register number. A hint type of zero specifies a register
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allocation preference. Other hint type values are target specific which are
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resolved by TargetRegisterInfo::ResolveRegAllocHint. An example is the ARM
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@ -675,7 +675,7 @@ it run faster:</p>
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by OS kernels.</li>
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<li>X86-64 now models implicit zero extensions better, which allows the code
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generator to remove a lot of redundant zexts. It also models the 8-bit "H"
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registers as sugregs, which allows they to be used in some tricky
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registers as sugregs, which allows them to be used in some tricky
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situations.</li>
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<li>X86-64 now supports the "local exec" and "initial exec" thread local storage
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model.</li>
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@ -741,8 +741,8 @@ supports both the Thumb2 and Advanced SIMD (Neon) instruction sets.</li>
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<li>The AAPCS-VFP "hard float" calling conventions are also supported with the
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<tt>-float-abi=hard</tt> flag.</li>
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<li>The ARM calling convention code is now tblgen generated instead of C++
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code.</li>
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<li>The ARM calling convention code is now tblgen generated instead of resorting
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to C++ code.</li>
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</li>
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