GlobalISel: handle G_SEQUENCE fallbacks gracefully.

There were two problems:
  + AArch64 was reusing random data from its binary op tables, which is
    complete nonsense for G_SEQUENCE.
  + Even when AArch64 gave up and said it couldn't handle G_SEQUENCE,
    the generic code asserted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288836 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/GlobalISel/RegBankSelect.cpp

@@ -367,6 +367,9 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping(
     const RegBankSelect::MappingCost *BestCost) {
   assert((MBFI || !BestCost) && "Costs comparison require MBFI");
 
+  if (!InstrMapping.isValid())
+    return MappingCost::ImpossibleCost();
+
   // If mapped with InstrMapping, MI will have the recorded cost.
   MappingCost Cost(MBFI ? MBFI->getBlockFreq(MI.getParent()) : 1);
   bool Saturated = Cost.addLocalCost(InstrMapping.getCost());

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

@@ -494,6 +494,10 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
                               AArch64::getCopyMapping(DstIsGPR, SrcIsGPR, Size),
                               /*NumOperands*/ 2};
   }
+  case TargetOpcode::G_SEQUENCE:
+    // FIXME: support this, but the generic code is really not going to do
+    // anything sane.
+    return InstructionMapping();
   default:
     break;
   }

test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll

@@ -59,9 +59,18 @@ false:
 
 }
 
+  ; General legalizer inability to handle types whose size wasn't a power of 2.
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type
 ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type:
 define void @odd_type(i42* %addr) {
   %val42 = load i42, i42* %addr
   ret void
 }
+
+  ; RegBankSelect crashed when given invalid mappings, and AArch64's
+  ; implementation produce valid-but-nonsense mappings for G_SEQUENCE.
+; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for sequence_mapping
+; FALLBACK-WITH-REPORT-OUT-LABEL: sequence_mapping:
+define void @sequence_mapping([2 x i64] %in) {
+  ret void
+}