From 3afd0d746deb4e9cf87bd2482a4564a5d8857d58 Mon Sep 17 00:00:00 2001
From: Dylan McKay <dylanmckay34@gmail.com>
Date: Sat, 31 Dec 2016 01:07:14 +0000
Subject: [PATCH] [AVR]  Optimize 16-bit ANDs with '1'

Summary: Fixes PR 31345

Reviewers: dylanmckay

Subscribers: fhahn, llvm-commits

Differential Revision: https://reviews.llvm.org/D28186

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290778 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/AVR/AVRExpandPseudoInsts.cpp |  4 ++
 test/CodeGen/AVR/PR31345.ll             | 51 +++++++++++++++++++++++++
 test/CodeGen/AVR/and.ll                 |  3 +-
 3 files changed, 57 insertions(+), 1 deletion(-)
 create mode 100644 test/CodeGen/AVR/PR31345.ll

diff --git a/lib/Target/AVR/AVRExpandPseudoInsts.cpp b/lib/Target/AVR/AVRExpandPseudoInsts.cpp
index 65a58cd31c3..1b2f2cec0bc 100644
--- a/lib/Target/AVR/AVRExpandPseudoInsts.cpp
+++ b/lib/Target/AVR/AVRExpandPseudoInsts.cpp
@@ -203,6 +203,10 @@ expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
 bool AVRExpandPseudo::
   isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const {
 
+  // ANDI Rd, 0xff is redundant.
+  if (Op == AVR::ANDIRdK && ImmVal == 0xff)
+    return true;
+
   // ORI Rd, 0x0 is redundant.
   if (Op == AVR::ORIRdK && ImmVal == 0x0)
     return true;
diff --git a/test/CodeGen/AVR/PR31345.ll b/test/CodeGen/AVR/PR31345.ll
new file mode 100644
index 00000000000..0d69fbc82ce
--- /dev/null
+++ b/test/CodeGen/AVR/PR31345.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+
+; Unit test for: PR 31345
+
+define i16 @and16_reg_imm_0xff00(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xff00
+; CHECK: andi {{r[0-9]+}}, 0
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+    %result = and i16 %a, 65280
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0xffb3(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xffb3
+; CHECK: andi {{r[0-9]+}}, 179
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+    %result = and i16 %a, 65459
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0x00ff(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0x00ff
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+; CHECK: andi {{r[0-9]+}}, 0
+    %result = and i16 %a, 255
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0xb3ff(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xb3ff
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+; CHECK: andi {{r[0-9]+}}, 179
+    %result = and i16 %a, 46079
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0xffff(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xffff
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+    %result = and i16 %a, 65535
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0xabcd(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xabcd
+; CHECK: andi {{r[0-9]+}}, 205
+; CHECK: andi {{r[0-9]+}}, 171
+    %result = and i16 %a, 43981
+    ret i16 %result
+}
diff --git a/test/CodeGen/AVR/and.ll b/test/CodeGen/AVR/and.ll
index 7f0e8ac2cba..de5bdf99284 100644
--- a/test/CodeGen/AVR/and.ll
+++ b/test/CodeGen/AVR/and.ll
@@ -67,7 +67,8 @@ define i64 @and64_reg_reg(i64 %a, i64 %b) {
 define i64 @and64_reg_imm(i64 %a) {
 ; CHECK-LABEL: and64_reg_imm:
 ; CHECK: andi r18, 253
-; CHECK: andi r19, 255
+; Per PR 31345, we optimize away ANDI Rd, 0xff
+; CHECK-NOT: andi r19, 255
 ; CHECK: andi r20, 155
 ; CHECK: andi r21, 88
 ; CHECK: andi r22, 76