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[AArch64] Improve codegen of store lane instructions by avoiding GPR usage.
We used to generate code similar to:
umov.b w8, v0[2]
strb w8, [x0, x1]
because the STR*ro* patterns were preferred to ST1*.
Instead, we can avoid going through GPRs, and generate:
add x8, x0, x1
st1.b { v0 }[2], [x8]
This patch increases the ST1* AddedComplexity to achieve that.
rdar://16372710
Differential Revision: http://reviews.llvm.org/D6202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225183 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha
parent
c52cd839b9
commit
3c9fb6e1ad
@ -4856,7 +4856,7 @@ defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
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defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
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defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
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let AddedComplexity = 15 in
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let AddedComplexity = 19 in
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class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
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ValueType VTy, ValueType STy, Instruction ST1>
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: Pat<(scalar_store
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@ -4872,7 +4872,7 @@ def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
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def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
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def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
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let AddedComplexity = 15 in
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let AddedComplexity = 19 in
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class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
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ValueType VTy, ValueType STy, Instruction ST1>
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: Pat<(scalar_store
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@ -8,10 +8,20 @@ define void @st1lane_16b(<16 x i8> %A, i8* %D) {
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ret void
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}
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define void @st1lane_ro_16b(<16 x i8> %A, i8* %D, i64 %offset) {
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; CHECK-LABEL: st1lane_ro_16b
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; CHECK: add x[[XREG:[0-9]+]], x0, x1
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; CHECK: st1.b { v0 }[1], [x[[XREG]]]
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%ptr = getelementptr i8* %D, i64 %offset
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%tmp = extractelement <16 x i8> %A, i32 1
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store i8 %tmp, i8* %ptr
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ret void
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}
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define void @st1lane0_ro_16b(<16 x i8> %A, i8* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_16b
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; CHECK: umov.b w[[WREG:[0-9]+]], v0[0]
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; CHECK: strb w[[WREG]], [x0, x1]
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; CHECK: add x[[XREG:[0-9]+]], x0, x1
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; CHECK: st1.b { v0 }[0], [x[[XREG]]]
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%ptr = getelementptr i8* %D, i64 %offset
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%tmp = extractelement <16 x i8> %A, i32 0
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store i8 %tmp, i8* %ptr
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@ -26,6 +36,16 @@ define void @st1lane_8h(<8 x i16> %A, i16* %D) {
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ret void
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}
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define void @st1lane_ro_8h(<8 x i16> %A, i16* %D, i64 %offset) {
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; CHECK-LABEL: st1lane_ro_8h
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; CHECK: add x[[XREG:[0-9]+]], x0, x1
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; CHECK: st1.h { v0 }[1], [x[[XREG]]]
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%ptr = getelementptr i16* %D, i64 %offset
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%tmp = extractelement <8 x i16> %A, i32 1
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store i16 %tmp, i16* %ptr
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ret void
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}
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define void @st1lane0_ro_8h(<8 x i16> %A, i16* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_8h
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; CHECK: str h0, [x0, x1, lsl #1]
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@ -43,6 +63,16 @@ define void @st1lane_4s(<4 x i32> %A, i32* %D) {
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ret void
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}
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define void @st1lane_ro_4s(<4 x i32> %A, i32* %D, i64 %offset) {
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; CHECK-LABEL: st1lane_ro_4s
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; CHECK: add x[[XREG:[0-9]+]], x0, x1
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; CHECK: st1.s { v0 }[1], [x[[XREG]]]
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%ptr = getelementptr i32* %D, i64 %offset
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%tmp = extractelement <4 x i32> %A, i32 1
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store i32 %tmp, i32* %ptr
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ret void
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}
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define void @st1lane0_ro_4s(<4 x i32> %A, i32* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_4s
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; CHECK: str s0, [x0, x1, lsl #2]
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@ -60,6 +90,16 @@ define void @st1lane_4s_float(<4 x float> %A, float* %D) {
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ret void
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}
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define void @st1lane_ro_4s_float(<4 x float> %A, float* %D, i64 %offset) {
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; CHECK-LABEL: st1lane_ro_4s_float
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; CHECK: add x[[XREG:[0-9]+]], x0, x1
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; CHECK: st1.s { v0 }[1], [x[[XREG]]]
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%ptr = getelementptr float* %D, i64 %offset
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%tmp = extractelement <4 x float> %A, i32 1
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store float %tmp, float* %ptr
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ret void
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}
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define void @st1lane0_ro_4s_float(<4 x float> %A, float* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_4s_float
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; CHECK: str s0, [x0, x1, lsl #2]
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@ -77,6 +117,16 @@ define void @st1lane_2d(<2 x i64> %A, i64* %D) {
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ret void
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}
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define void @st1lane_ro_2d(<2 x i64> %A, i64* %D, i64 %offset) {
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; CHECK-LABEL: st1lane_ro_2d
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; CHECK: add x[[XREG:[0-9]+]], x0, x1
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; CHECK: st1.d { v0 }[1], [x[[XREG]]]
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%ptr = getelementptr i64* %D, i64 %offset
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%tmp = extractelement <2 x i64> %A, i32 1
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store i64 %tmp, i64* %ptr
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ret void
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}
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define void @st1lane0_ro_2d(<2 x i64> %A, i64* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_2d
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; CHECK: str d0, [x0, x1, lsl #3]
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@ -94,6 +144,16 @@ define void @st1lane_2d_double(<2 x double> %A, double* %D) {
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ret void
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}
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define void @st1lane_ro_2d_double(<2 x double> %A, double* %D, i64 %offset) {
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; CHECK-LABEL: st1lane_ro_2d_double
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; CHECK: add x[[XREG:[0-9]+]], x0, x1
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; CHECK: st1.d { v0 }[1], [x[[XREG]]]
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%ptr = getelementptr double* %D, i64 %offset
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%tmp = extractelement <2 x double> %A, i32 1
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store double %tmp, double* %ptr
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ret void
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}
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define void @st1lane0_ro_2d_double(<2 x double> %A, double* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_2d_double
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; CHECK: str d0, [x0, x1, lsl #3]
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@ -111,10 +171,20 @@ define void @st1lane_8b(<8 x i8> %A, i8* %D) {
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ret void
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}
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define void @st1lane_ro_8b(<8 x i8> %A, i8* %D, i64 %offset) {
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; CHECK-LABEL: st1lane_ro_8b
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; CHECK: add x[[XREG:[0-9]+]], x0, x1
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; CHECK: st1.b { v0 }[1], [x[[XREG]]]
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%ptr = getelementptr i8* %D, i64 %offset
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%tmp = extractelement <8 x i8> %A, i32 1
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store i8 %tmp, i8* %ptr
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ret void
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}
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define void @st1lane0_ro_8b(<8 x i8> %A, i8* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_8b
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; CHECK: umov.b w[[WREG:[0-9]+]], v0[0]
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; CHECK: strb w[[WREG]], [x0, x1]
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; CHECK: add x[[XREG:[0-9]+]], x0, x1
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; CHECK: st1.b { v0 }[0], [x[[XREG]]]
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%ptr = getelementptr i8* %D, i64 %offset
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%tmp = extractelement <8 x i8> %A, i32 0
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store i8 %tmp, i8* %ptr
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@ -129,6 +199,16 @@ define void @st1lane_4h(<4 x i16> %A, i16* %D) {
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ret void
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}
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define void @st1lane_ro_4h(<4 x i16> %A, i16* %D, i64 %offset) {
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; CHECK-LABEL: st1lane_ro_4h
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; CHECK: add x[[XREG:[0-9]+]], x0, x1
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; CHECK: st1.h { v0 }[1], [x[[XREG]]]
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%ptr = getelementptr i16* %D, i64 %offset
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%tmp = extractelement <4 x i16> %A, i32 1
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store i16 %tmp, i16* %ptr
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ret void
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}
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define void @st1lane0_ro_4h(<4 x i16> %A, i16* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_4h
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; CHECK: str h0, [x0, x1, lsl #1]
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@ -146,6 +226,16 @@ define void @st1lane_2s(<2 x i32> %A, i32* %D) {
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ret void
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}
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define void @st1lane_ro_2s(<2 x i32> %A, i32* %D, i64 %offset) {
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; CHECK-LABEL: st1lane_ro_2s
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; CHECK: add x[[XREG:[0-9]+]], x0, x1
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; CHECK: st1.s { v0 }[1], [x[[XREG]]]
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%ptr = getelementptr i32* %D, i64 %offset
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%tmp = extractelement <2 x i32> %A, i32 1
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store i32 %tmp, i32* %ptr
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ret void
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}
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define void @st1lane0_ro_2s(<2 x i32> %A, i32* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_2s
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; CHECK: str s0, [x0, x1, lsl #2]
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@ -163,6 +253,16 @@ define void @st1lane_2s_float(<2 x float> %A, float* %D) {
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ret void
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}
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define void @st1lane_ro_2s_float(<2 x float> %A, float* %D, i64 %offset) {
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; CHECK-LABEL: st1lane_ro_2s_float
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; CHECK: add x[[XREG:[0-9]+]], x0, x1
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; CHECK: st1.s { v0 }[1], [x[[XREG]]]
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%ptr = getelementptr float* %D, i64 %offset
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%tmp = extractelement <2 x float> %A, i32 1
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store float %tmp, float* %ptr
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ret void
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}
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define void @st1lane0_ro_2s_float(<2 x float> %A, float* %D, i64 %offset) {
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; CHECK-LABEL: st1lane0_ro_2s_float
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; CHECK: str s0, [x0, x1, lsl #2]
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