From 3cc160451c32c1dc636a679d03a8b24962496eed Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 10 Nov 2016 14:19:45 +0000 Subject: [PATCH] [DAGCombiner] Show missed opportunity to UNDEF out-of-range SHL Fails to match constant shift value due to presence of AND mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286452 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/combine-shl.ll | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/test/CodeGen/X86/combine-shl.ll b/test/CodeGen/X86/combine-shl.ll index 64ed1cea8d4..a35a30927a8 100644 --- a/test/CodeGen/X86/combine-shl.ll +++ b/test/CodeGen/X86/combine-shl.ll @@ -44,6 +44,21 @@ define <4 x i32> @combine_vec_shl_outofrange1(<4 x i32> %x) { ret <4 x i32> %1 } +define <4 x i32> @combine_vec_shl_outofrange2(<4 x i32> %a0) { +; SSE-LABEL: combine_vec_shl_outofrange2: +; SSE: # BB#0: +; SSE-NEXT: xorps %xmm0, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: combine_vec_shl_outofrange2: +; AVX: # BB#0: +; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; AVX-NEXT: retq + %1 = and <4 x i32> %a0, + %2 = shl <4 x i32> %1, + ret <4 x i32> %2 +} + ; fold (shl x, 0) -> x define <4 x i32> @combine_vec_shl_by_zero(<4 x i32> %x) { ; SSE-LABEL: combine_vec_shl_by_zero: