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[X86] Add BMI2 scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308136 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
parent
6294089b16
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180
test/CodeGen/X86/bmi2-schedule.ll
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180
test/CodeGen/X86/bmi2-schedule.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mattr=+bmi2 | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=knl | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=CHECK --check-prefix=ZNVER1
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define i32 @test_bzhi_i32(i32 %a0, i32 %a1, i32 *%a2) {
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; GENERIC-LABEL: test_bzhi_i32:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: bzhil %edi, (%rdx), %ecx
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; GENERIC-NEXT: bzhil %edi, %esi, %eax
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; GENERIC-NEXT: addl %ecx, %eax
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; GENERIC-NEXT: retq
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;
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; HASWELL-LABEL: test_bzhi_i32:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: bzhil %edi, (%rdx), %ecx # sched: [4:0.50]
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; HASWELL-NEXT: bzhil %edi, %esi, %eax # sched: [1:0.50]
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; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_bzhi_i32:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: bzhil %edi, (%rdx), %ecx # sched: [?:0.000000e+00]
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; ZNVER1-NEXT: bzhil %edi, %esi, %eax # sched: [?:0.000000e+00]
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; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.50]
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; ZNVER1-NEXT: retq # sched: [4:1.00]
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%1 = load i32, i32 *%a2
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%2 = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %1, i32 %a0)
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%3 = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %a1, i32 %a0)
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%4 = add i32 %2, %3
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ret i32 %4
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}
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declare i32 @llvm.x86.bmi.bzhi.32(i32, i32)
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define i64 @test_bzhi_i64(i64 %a0, i64 %a1, i64 *%a2) {
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; GENERIC-LABEL: test_bzhi_i64:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: bzhiq %rdi, (%rdx), %rcx
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; GENERIC-NEXT: bzhiq %rdi, %rsi, %rax
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; GENERIC-NEXT: addq %rcx, %rax
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; GENERIC-NEXT: retq
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;
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; HASWELL-LABEL: test_bzhi_i64:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [4:0.50]
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; HASWELL-NEXT: bzhiq %rdi, %rsi, %rax # sched: [1:0.50]
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; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_bzhi_i64:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [?:0.000000e+00]
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; ZNVER1-NEXT: bzhiq %rdi, %rsi, %rax # sched: [?:0.000000e+00]
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; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.50]
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; ZNVER1-NEXT: retq # sched: [4:1.00]
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%1 = load i64, i64 *%a2
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%2 = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %1, i64 %a0)
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%3 = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %a1, i64 %a0)
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%4 = add i64 %2, %3
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ret i64 %4
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}
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declare i64 @llvm.x86.bmi.bzhi.64(i64, i64)
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define i32 @test_pdep_i32(i32 %a0, i32 %a1, i32 *%a2) {
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; GENERIC-LABEL: test_pdep_i32:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: pdepl (%rdx), %edi, %ecx
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; GENERIC-NEXT: pdepl %esi, %edi, %eax
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; GENERIC-NEXT: addl %ecx, %eax
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; GENERIC-NEXT: retq
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;
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; HASWELL-LABEL: test_pdep_i32:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: pdepl (%rdx), %edi, %ecx # sched: [7:1.00]
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; HASWELL-NEXT: pdepl %esi, %edi, %eax # sched: [3:1.00]
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; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_pdep_i32:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: pdepl (%rdx), %edi, %ecx # sched: [?:0.000000e+00]
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; ZNVER1-NEXT: pdepl %esi, %edi, %eax # sched: [?:0.000000e+00]
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; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.50]
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; ZNVER1-NEXT: retq # sched: [4:1.00]
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%1 = load i32, i32 *%a2
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%2 = tail call i32 @llvm.x86.bmi.pdep.32(i32 %a0, i32 %1)
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%3 = tail call i32 @llvm.x86.bmi.pdep.32(i32 %a0, i32 %a1)
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%4 = add i32 %2, %3
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ret i32 %4
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}
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declare i32 @llvm.x86.bmi.pdep.32(i32, i32)
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define i64 @test_pdep_i64(i64 %a0, i64 %a1, i64 *%a2) {
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; GENERIC-LABEL: test_pdep_i64:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: pdepq (%rdx), %rdi, %rcx
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; GENERIC-NEXT: pdepq %rsi, %rdi, %rax
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; GENERIC-NEXT: addq %rcx, %rax
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; GENERIC-NEXT: retq
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;
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; HASWELL-LABEL: test_pdep_i64:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: pdepq (%rdx), %rdi, %rcx # sched: [7:1.00]
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; HASWELL-NEXT: pdepq %rsi, %rdi, %rax # sched: [3:1.00]
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; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_pdep_i64:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: pdepq (%rdx), %rdi, %rcx # sched: [?:0.000000e+00]
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; ZNVER1-NEXT: pdepq %rsi, %rdi, %rax # sched: [?:0.000000e+00]
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; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.50]
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; ZNVER1-NEXT: retq # sched: [4:1.00]
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%1 = load i64, i64 *%a2
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%2 = tail call i64 @llvm.x86.bmi.pdep.64(i64 %a0, i64 %1)
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%3 = tail call i64 @llvm.x86.bmi.pdep.64(i64 %a0, i64 %a1)
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%4 = add i64 %2, %3
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ret i64 %4
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}
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declare i64 @llvm.x86.bmi.pdep.64(i64, i64)
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define i32 @test_pext_i32(i32 %a0, i32 %a1, i32 *%a2) {
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; GENERIC-LABEL: test_pext_i32:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: pextl (%rdx), %edi, %ecx
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; GENERIC-NEXT: pextl %esi, %edi, %eax
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; GENERIC-NEXT: addl %ecx, %eax
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; GENERIC-NEXT: retq
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;
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; HASWELL-LABEL: test_pext_i32:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: pextl (%rdx), %edi, %ecx # sched: [7:1.00]
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; HASWELL-NEXT: pextl %esi, %edi, %eax # sched: [3:1.00]
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; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_pext_i32:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: pextl (%rdx), %edi, %ecx # sched: [?:0.000000e+00]
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; ZNVER1-NEXT: pextl %esi, %edi, %eax # sched: [?:0.000000e+00]
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; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.50]
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; ZNVER1-NEXT: retq # sched: [4:1.00]
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%1 = load i32, i32 *%a2
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%2 = tail call i32 @llvm.x86.bmi.pext.32(i32 %a0, i32 %1)
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%3 = tail call i32 @llvm.x86.bmi.pext.32(i32 %a0, i32 %a1)
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%4 = add i32 %2, %3
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ret i32 %4
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}
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declare i32 @llvm.x86.bmi.pext.32(i32, i32)
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define i64 @test_pext_i64(i64 %a0, i64 %a1, i64 *%a2) {
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; GENERIC-LABEL: test_pext_i64:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: pextq (%rdx), %rdi, %rcx
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; GENERIC-NEXT: pextq %rsi, %rdi, %rax
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; GENERIC-NEXT: addq %rcx, %rax
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; GENERIC-NEXT: retq
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;
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; HASWELL-LABEL: test_pext_i64:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: pextq (%rdx), %rdi, %rcx # sched: [7:1.00]
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; HASWELL-NEXT: pextq %rsi, %rdi, %rax # sched: [3:1.00]
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; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_pext_i64:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: pextq (%rdx), %rdi, %rcx # sched: [?:0.000000e+00]
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; ZNVER1-NEXT: pextq %rsi, %rdi, %rax # sched: [?:0.000000e+00]
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; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.50]
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; ZNVER1-NEXT: retq # sched: [4:1.00]
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%1 = load i64, i64 *%a2
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%2 = tail call i64 @llvm.x86.bmi.pext.64(i64 %a0, i64 %1)
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%3 = tail call i64 @llvm.x86.bmi.pext.64(i64 %a0, i64 %a1)
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%4 = add i64 %2, %3
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ret i64 %4
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}
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declare i64 @llvm.x86.bmi.pext.64(i64, i64)
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