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[Power9] Add patterns for vnegd, vnegw

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Exploit new instructions by adding patterns to .td file.
https://reviews.llvm.org/D26551



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287334 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ehsan Amiri 2016-11-18 11:05:55 +00:00
parent 9f23214cb5
commit 3d73fcad55
2 changed files with 29 additions and 2 deletions
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9
lib/Target/PowerPC/PPCInstrAltivec.td
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@ -1315,8 +1315,13 @@ let isCodeGenOnly = 1 in {
}
// Vector Integer Negate
def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", []>;
def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", []>;
def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw",
[(set v4i32:$vD,
(sub (v4i32 immAllZerosV), v4i32:$vB))]>;
def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd",
[(set v2i64:$vD,
(sub (v2i64 (bitconvert (v4i32 immAllZerosV))), v2i64:$vB))]>;
// Vector Parity Byte
def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD,

22
test/CodeGen/PowerPC/vsx-p9.ll
View File

@ -388,4 +388,26 @@ entry:
; Function Attrs: nounwind readnone
declare void @llvm.ppc.vsx.stxvll(<4 x i32>, i8*, i64)
define <4 x i32> @test0(<4 x i32> %a) local_unnamed_addr #0 {
entry:
%sub.i = sub <4 x i32> zeroinitializer, %a
ret <4 x i32> %sub.i
; CHECK-LABEL: @test0
; CHECK: vnegw 2, 2
; CHECK: blr
}
define <2 x i64> @test1(<2 x i64> %a) local_unnamed_addr #0 {
entry:
%sub.i = sub <2 x i64> zeroinitializer, %a
ret <2 x i64> %sub.i
; CHECK-LABEL: @test1
; CHECK: vnegd 2, 2
; CHECK: blr
}
declare void @sink(...)