mirror of
https://github.com/RPCSX/llvm.git
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[Hexagon] Adding gp+ to the syntax of gp-relative instructions
Patch by Colin LeMahieu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294258 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
0887cb0d09
commit
3d7650ecd0
@ -2142,6 +2142,62 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
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Inst = TmpInst;
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break;
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}
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case Hexagon::PS_loadrubabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
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Inst.setOpcode(Hexagon::L2_loadrubgp);
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break;
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case Hexagon::PS_loadrbabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
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Inst.setOpcode(Hexagon::L2_loadrbgp);
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break;
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case Hexagon::PS_loadruhabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
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Inst.setOpcode(Hexagon::L2_loadruhgp);
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break;
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case Hexagon::PS_loadrhabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
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Inst.setOpcode(Hexagon::L2_loadrhgp);
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break;
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case Hexagon::PS_loadriabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
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Inst.setOpcode(Hexagon::L2_loadrigp);
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break;
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case Hexagon::PS_loadrdabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
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Inst.setOpcode(Hexagon::L2_loadrdgp);
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break;
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case Hexagon::PS_storerbabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
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Inst.setOpcode(Hexagon::S2_storerbgp);
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break;
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case Hexagon::PS_storerhabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
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Inst.setOpcode(Hexagon::S2_storerhgp);
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break;
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case Hexagon::PS_storerfabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
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Inst.setOpcode(Hexagon::S2_storerfgp);
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break;
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case Hexagon::PS_storeriabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
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Inst.setOpcode(Hexagon::S2_storerigp);
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break;
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case Hexagon::PS_storerdabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
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Inst.setOpcode(Hexagon::S2_storerdgp);
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break;
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case Hexagon::PS_storerbnewabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
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Inst.setOpcode(Hexagon::S2_storerbnewgp);
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break;
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case Hexagon::PS_storerhnewabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
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Inst.setOpcode(Hexagon::S2_storerhnewgp);
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break;
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case Hexagon::PS_storerinewabs:
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if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
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Inst.setOpcode(Hexagon::S2_storerinewgp);
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break;
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} // switch
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return Match_Success;
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@ -2532,7 +2532,7 @@ let hasSideEffects = 0, isPredicable = 1 in
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class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
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bits<2>MajOp, bit isAbs, bit isHalf>
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: STInst<(outs), (ins ImmOp:$addr, RC:$src),
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mnemonic # "(#$addr) = $src"#!if(isHalf, ".h",""),
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mnemonic # "(" # !if(isAbs,"","gp+") # "#$addr) = $src" # !if(isHalf,".h",""),
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[], "", V2LDST_tc_st_SLOT01> {
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bits<19> addr;
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bits<5> src;
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@ -2646,9 +2646,9 @@ multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
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isNewValue = 1, opNewValue = 1 in
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class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp>
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class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
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: NVInst_V4<(outs), (ins ImmOp:$addr, IntRegs:$src),
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mnemonic #"(#$addr) = $src.new",
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mnemonic #"(" # !if(isAbs, "", "gp+") # "#$addr) = $src.new",
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[], "", V2LDST_tc_st_SLOT0> {
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bits<19> addr;
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bits<3> src;
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@ -2716,7 +2716,7 @@ class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
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// absolute addressing.
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//===----------------------------------------------------------------------===//
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class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
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: T_StoreAbsGP_NV <mnemonic, u32_0MustExt, MajOp>, AddrModeRel {
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: T_StoreAbsGP_NV <mnemonic, u32_0MustExt, MajOp, 1>, AddrModeRel {
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string ImmOpStr = !cast<string>(ImmOp);
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let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
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@ -2798,7 +2798,7 @@ multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
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def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
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0, isHalf>;
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// New-value store
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def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp> ;
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def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
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}
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}
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@ -2825,9 +2825,9 @@ def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
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//===----------------------------------------------------------------------===//
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let isPredicable = 1, hasSideEffects = 0 in
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class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
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bits<3> MajOp>
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bits<3> MajOp, bit isAbs>
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: LDInst <(outs RC:$dst), (ins ImmOp:$addr),
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"$dst = "#mnemonic# "(#$addr)",
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"$dst = " # mnemonic # "(" # !if(isAbs, "", "gp+") # "#$addr)",
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[], "", V2LDST_tc_ld_SLOT01> {
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bits<5> dst;
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bits<19> addr;
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@ -2860,7 +2860,7 @@ class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
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class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
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bits<3> MajOp>
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: T_LoadAbsGP <mnemonic, RC, u32_0MustExt, MajOp>, AddrModeRel {
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: T_LoadAbsGP <mnemonic, RC, u32_0MustExt, MajOp, 1>, AddrModeRel {
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string ImmOpStr = !cast<string>(ImmOp);
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let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
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@ -2956,7 +2956,7 @@ defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
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let isAsmParserOnly = 1, Uses = [GP] in
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class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
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bits<3> MajOp>
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: T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp>, PredNewRel {
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: T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, 0>, PredNewRel {
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let BaseOpcode = BaseOp#_abs;
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}
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@ -54,9 +54,9 @@ entry:
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}
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; CHECK-LABEL: test3
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; CHECK: [[REG31:(r[0-9]+)]]{{ *}}={{ *}}memw(#b)
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; CHECK: [[REG31:(r[0-9]+)]]{{ *}}={{ *}}memw(gp+#b)
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; CHECK: [[REG32:(r[0-9]+)]] = sfadd({{.*}}[[REG31]]
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; CHECK: memw(#a) = [[REG32]]
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; CHECK: memw(gp+#a) = [[REG32]]
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; Function Attrs: norecurse nounwind
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define void @test3(%struct.matrix_params* nocapture readonly %params, i32 %col1) {
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@ -7,8 +7,8 @@
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define i32 @foo(i32 %p) #0 {
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entry:
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#a)
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#b)
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(gp+#a)
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(gp+#b)
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; CHECK: if{{ *}}(p{{[0-3]}}) memw(##c){{ *}}={{ *}}r{{[0-9]+}}
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%0 = load i32, i32* @a, align 4
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%1 = load i32, i32* @b, align 4
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@ -8,13 +8,13 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK-LABEL: foo
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; CHECK-DAG: memw(##b)
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; CHECK-DAG: memw(#d)
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; CHECK-DAG: memw(gp+#d)
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; CHECK-DAG: memw(##g)
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; CHECK-DAG: memw(#h)
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; CHECK-DAG: memw(#f)
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; CHECK-DAG: memw(gp+#h)
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; CHECK-DAG: memw(gp+#f)
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; CHECK-DAG: memw(##e)
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; CHECK-DAG: memw(#a)
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; CHECK-DAG: memw(#c)
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; CHECK-DAG: memw(gp+#a)
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; CHECK-DAG: memw(gp+#c)
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; CHECK-LABEL: bar
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; CHECK: memw(##b)
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@ -4,9 +4,9 @@
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@acc = external global i32
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@val = external global i32
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; CHECK-DAG: memw(#num)
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; CHECK-DAG: memw(#acc)
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; CHECK-DAG: memw(#val)
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; CHECK-DAG: memw(gp+#num)
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; CHECK-DAG: memw(gp+#acc)
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; CHECK-DAG: memw(gp+#val)
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define void @foo() nounwind {
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entry:
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@ -5,7 +5,7 @@
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0x90 0xff 0xd5 0x3a
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# CHECK: r17:16 = memd(r21 + r31<<#3)
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0xb0 0xc2 0xc0 0x49
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# CHECK: r17:16 = memd(#168)
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# CHECK: r17:16 = memd(gp+#168)
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0x02 0x40 0x00 0x00 0x10 0xc5 0xc0 0x49
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# CHECK: r17:16 = memd(##168)
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0xd0 0xc0 0xd5 0x91
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@ -59,7 +59,7 @@
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0x91 0xff 0x15 0x3a
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# CHECK: r17 = memb(r21 + r31<<#3)
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0xb1 0xc2 0x00 0x49
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# CHECK: r17 = memb(#21)
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# CHECK: r17 = memb(gp+#21)
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0x00 0x40 0x00 0x00 0xb1 0xc2 0x00 0x49
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# CHECK: r17 = memb(##21)
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0xf1 0xc3 0x15 0x91
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@ -129,7 +129,7 @@
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0x91 0xff 0x55 0x3a
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# CHECK: r17 = memh(r21 + r31<<#3)
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0xb1 0xc2 0x40 0x49
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# CHECK: r17 = memh(#42)
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# CHECK: r17 = memh(gp+#42)
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0x00 0x40 0x00 0x00 0x51 0xc5 0x40 0x49
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# CHECK: r17 = memh(##42)
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0xf1 0xc3 0x55 0x91
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@ -183,7 +183,7 @@
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0x91 0xff 0x35 0x3a
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# CHECK: r17 = memub(r21 + r31<<#3)
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0xb1 0xc2 0x20 0x49
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# CHECK: r17 = memub(#21)
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# CHECK: r17 = memub(gp+#21)
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0x00 0x40 0x00 0x00 0xb1 0xc2 0x20 0x49
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# CHECK: r17 = memub(##21)
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0xf1 0xc3 0x35 0x91
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@ -237,7 +237,7 @@
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0x91 0xff 0x75 0x3a
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# CHECK: r17 = memuh(r21 + r31<<#3)
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0xb1 0xc2 0x60 0x49
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# CHECK: r17 = memuh(#42)
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# CHECK: r17 = memuh(gp+#42)
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0x00 0x40 0x00 0x00 0x51 0xc5 0x60 0x49
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# CHECK: r17 = memuh(##42)
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0xb1 0xc2 0x75 0x91
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@ -291,7 +291,7 @@
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0x91 0xff 0x95 0x3a
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# CHECK: r17 = memw(r21 + r31<<#3)
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0xb1 0xc2 0x80 0x49
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# CHECK: r17 = memw(#84)
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# CHECK: r17 = memw(gp+#84)
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0x01 0x40 0x00 0x00 0x91 0xc2 0x80 0x49
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# CHECK: r17 = memw(##84)
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0xb1 0xc2 0x95 0x91
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@ -7,7 +7,7 @@
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# CHECK-NEXT: memb(r17 + r21<<#3) = r31.new
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0x1f 0x40 0x7f 0x70 0x11 0xc2 0xa0 0x48
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# CHECK: r31 = r31
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# CHECK-NEXT: memb(#17) = r31.new
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# CHECK-NEXT: memb(gp+#17) = r31.new
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0x1f 0x40 0x7f 0x70 0x15 0xc2 0xb1 0xa1
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# CHECK: r31 = r31
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# CHECK-NEXT: memb(r17+#21) = r31.new
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@ -77,7 +77,7 @@
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# CHECK-NEXT: memh(r17 + r21<<#3) = r31.new
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0x1f 0x40 0x7f 0x70 0x15 0xca 0xa0 0x48
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# CHECK: r31 = r31
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# CHECK-NEXT: memh(#42) = r31.new
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# CHECK-NEXT: memh(gp+#42) = r31.new
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0x1f 0x40 0x7f 0x70 0x15 0xca 0xb1 0xa1
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# CHECK: r31 = r31
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# CHECK-NEXT: memh(r17+#42) = r31.new
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@ -147,7 +147,7 @@
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# CHECK-NEXT: memw(r17 + r21<<#3) = r31.new
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0x1f 0x40 0x7f 0x70 0x15 0xd2 0xa0 0x48
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# CHECK: r31 = r31
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# CHECK-NEXT: memw(#84) = r31.new
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# CHECK-NEXT: memw(gp+#84) = r31.new
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0x1f 0x40 0x7f 0x70 0x15 0xd2 0xb1 0xa1
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# CHECK: r31 = r31
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# CHECK-NEXT: memw(r17+#84) = r31.new
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@ -5,7 +5,7 @@
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0x9e 0xf5 0xd1 0x3b
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# CHECK: memd(r17 + r21<<#3) = r31:30
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0x28 0xd4 0xc0 0x48
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# CHECK: memd(#320) = r21:20
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# CHECK: memd(gp+#320) = r21:20
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0x02 0x40 0x00 0x00 0x28 0xd4 0xc0 0x48
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# CHECK: memd(##168) = r21:20
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0x15 0xd4 0xd1 0xa1
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@ -71,7 +71,7 @@
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0x9f 0xca 0x11 0x3c
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# CHECK: memb(r17+#21)=#31
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0x15 0xd5 0x00 0x48
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# CHECK: memb(#21) = r21
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# CHECK: memb(gp+#21) = r21
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0x00 0x40 0x00 0x00 0x15 0xd5 0x00 0x48
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# CHECK: memb(##21) = r21
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0x15 0xd5 0x11 0xa1
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@ -153,9 +153,9 @@
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0x00 0x40 0x00 0x00 0x2a 0xd5 0x60 0x48
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# CHECK: memh(##42) = r21.h
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0x2a 0xd5 0x40 0x48
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# CHECK: memh(#84) = r21
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# CHECK: memh(gp+#84) = r21
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0x2a 0xd5 0x60 0x48
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# CHECK: memh(#84) = r21.h
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# CHECK: memh(gp+#84) = r21.h
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0x15 0xdf 0x51 0xa1
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# CHECK: memh(r17+#42) = r31
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0x15 0xdf 0x71 0xa1
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@ -283,7 +283,7 @@
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0x9f 0xca 0x51 0x3c
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# CHECK: memw(r17{{ *}}+{{ *}}#84)=#31
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0x15 0xdf 0x80 0x48
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# CHECK: memw(#84) = r31
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# CHECK: memw(gp+#84) = r31
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0x01 0x40 0x00 0x00 0x14 0xd5 0x80 0x48
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# CHECK: memw(##84) = r21
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0x9f 0xca 0x51 0x3c
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150
test/MC/Hexagon/decode_acc_type.s
Normal file
150
test/MC/Hexagon/decode_acc_type.s
Normal file
@ -0,0 +1,150 @@
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# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
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#
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# Currently ignore if there is one or two #'s
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r7 = memw(gp+#192)
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# CHECK: r7 = memw(gp+#192)
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r3:2 = memd(gp+#64)
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# CHECK: r3:2 = memd(gp+#64)
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{ p3 = p1; r8 = #2; if (p3.new) memw(##8) = r8.new }
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# CHECK: if (p3.new) memw({{..}}8) = r8
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{ p3 = p1; r8 = #2; if (!p3.new) memw(##8) = r8.new }
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# CHECK: if (!p3.new) memw({{..}}8) = r8.new
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{ r8 = #2; if (p3) memw(##8) = r8.new }
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# CHECK: if (p3) memw({{..}}8) = r8.new
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{ r8 = #2; if (!p3) memw(##8) = r8.new }
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# CHECK: if (!p3) memw({{..}}8) = r8.new
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{ p3 = p1; r8 = #2; if (p3.new) memh(##8) = r8.new }
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# CHECK: if (p3.new) memh({{..}}8) = r8.new
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{ p3 = p1; r8 = #2; if (!p3.new) memh(##8) = r8.new }
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# CHECK: if (!p3.new) memh({{..}}8) = r8.new
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{ r8 = #2; if (p3) memh(##8) = r8.new }
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# CHECK: memh({{..}}8) = r8.new
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{ r8 = #2; if (!p3) memh(##8) = r8.new }
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# CHECK: if (!p3) memh({{..}}8) = r8.new
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|
||||
{ p3 = p1; r8 = #2; if (p3.new) memb(##8) = r8.new }
|
||||
# CHECK: if (p3.new) memb({{..}}8) = r8.new
|
||||
|
||||
{ p3 = p1; r8 = #2; if (!p3.new) memb(##8) = r8.new }
|
||||
# CHECK: if (!p3.new) memb({{..}}8) = r8.new
|
||||
|
||||
{ r8 = #2; if (p3) memb(##8) = r8.new }
|
||||
# CHECK: if (p3) memb({{..}}8) = r8.new
|
||||
|
||||
{ r8 = #2; if (!p3) memb(##8) = r8.new }
|
||||
# CHECK: if (!p3) memb({{..}}8) = r8.new
|
||||
|
||||
{ if (p3) memw(##8) = r8 }
|
||||
# CHECK: if (p3) memw({{..}}8) = r8
|
||||
|
||||
{ if (!p3) memw(##8) = r8 }
|
||||
# CHECK: if (!p3) memw({{..}}8) = r8
|
||||
|
||||
{ p3 = p1; if (p3.new) memw(##8) = r8 }
|
||||
# CHECK: if (p3.new) memw({{..}}8) = r8
|
||||
|
||||
{ p3 = p1; if (!p3.new) memw(##8) = r8 }
|
||||
# CHECK: if (!p3.new) memw({{..}}8) = r8
|
||||
|
||||
|
||||
if (!p2) r14 = memb(##48)
|
||||
# CHECK: if (!p2) r14 = memb({{..}}48)
|
||||
|
||||
if (p2) r14 = memb(##48)
|
||||
# CHECK: if (p2) r14 = memb({{..}}48)
|
||||
|
||||
{p2 = p0; if (!p2.new) r14 = memb(##48) }
|
||||
# CHECK: if (!p2.new) r14 = memb({{..}}48)
|
||||
|
||||
{p3 = p2; if (p3.new) r14 = memb(##48) }
|
||||
# CHECK: if (p3.new) r14 = memb({{..}}48)
|
||||
|
||||
|
||||
if (!p2) r14 = memh(##48)
|
||||
# CHECK: if (!p2) r14 = memh({{..}}48)
|
||||
|
||||
if (p2) r14 = memh(##48)
|
||||
# CHECK: if (p2) r14 = memh({{..}}48)
|
||||
|
||||
{p2 = p0; if (!p2.new) r14 = memh(##48) }
|
||||
# CHECK: if (!p2.new) r14 = memh({{..}}48)
|
||||
|
||||
{p3 = p2; if (p3.new) r14 = memh(##48) }
|
||||
# CHECK: if (p3.new) r14 = memh({{..}}48)
|
||||
|
||||
|
||||
if (!p2) r14 = memub(##48)
|
||||
# CHECK: if (!p2) r14 = memub({{..}}48)
|
||||
|
||||
if (p2) r14 = memub(##48)
|
||||
# CHECK: if (p2) r14 = memub({{..}}48)
|
||||
|
||||
{p2 = p0; if (!p2.new) r14 = memub(##48) }
|
||||
# CHECK: if (!p2.new) r14 = memub({{..}}48)
|
||||
|
||||
{p3 = p2; if (p3.new) r14 = memub(##48) }
|
||||
# CHECK: if (p3.new) r14 = memub({{..}}48)
|
||||
|
||||
|
||||
if (!p2) r14 = memuh(##48)
|
||||
# CHECK: if (!p2) r14 = memuh({{..}}48)
|
||||
|
||||
if (p2) r14 = memuh(##48)
|
||||
# CHECK: if (p2) r14 = memuh({{..}}48)
|
||||
|
||||
{p2 = p0; if (!p2.new) r14 = memuh(##48) }
|
||||
# CHECK: if (!p2.new) r14 = memuh({{..}}48)
|
||||
|
||||
{p3 = p2; if (p3.new) r14 = memuh(##48) }
|
||||
# CHECK: r14 = memuh({{..}}48)
|
||||
|
||||
|
||||
if (!p2) r14 = memw(##48)
|
||||
# CHECK: if (!p2) r14 = memw({{..}}48)
|
||||
|
||||
if (p2) r14 = memw(##48)
|
||||
# CHECK: if (p2) r14 = memw({{..}}48)
|
||||
|
||||
{p2 = p0; if (!p2.new) r14 = memw(##48) }
|
||||
# CHECK: if (!p2.new) r14 = memw({{..}}48)
|
||||
|
||||
{p3 = p2; if (p3.new) r14 = memw(##48) }
|
||||
# CHECK: if (p3.new) r14 = memw({{..}}48)
|
||||
|
||||
r7 = memh(##32)
|
||||
# CHECK: r7 = memh(##32)
|
||||
r7 = memuh(##32)
|
||||
# CHECK: r7 = memuh(##32)
|
||||
|
||||
memd(##32) = r15:14
|
||||
# CHECK: memd(##32) = r15:14
|
||||
|
||||
{r2 = #9; memw(##32) = r2.new}
|
||||
# CHECK: memw(##32) = r2.new
|
||||
|
||||
{r2 = #9; memb(##32) = r2.new}
|
||||
# CHECK: memb(##32) = r2.new
|
||||
|
||||
memw(##32) = r15
|
||||
# CHECK: memw(##32) = r15
|
||||
|
||||
memh(##32) = r16
|
||||
# CHECK: memh(##32) = r16
|
||||
|
||||
memb(##32) = r17
|
||||
# CHECK: memb(##32) = r17
|
||||
|
||||
|
||||
r3:2 = interleave(r31:30)
|
||||
# CHECK: r3:2 = interleave(r31:30)
|
||||
210
test/MC/Hexagon/extender.s
Normal file
210
test/MC/Hexagon/extender.s
Normal file
@ -0,0 +1,210 @@
|
||||
# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
|
||||
#
|
||||
|
||||
# STrib_abs_V4
|
||||
{
|
||||
memb(##1024056) = r0
|
||||
}
|
||||
|
||||
# CHECK: immext(#1024000)
|
||||
# CHECK: memb(##1024056) = r0
|
||||
|
||||
# S2_storerbgp
|
||||
{
|
||||
memb(GP + #56) = r0
|
||||
}
|
||||
|
||||
# CHECK: memb(gp+#56) = r0
|
||||
|
||||
# STrih_abs_V4
|
||||
{
|
||||
memh(##1024056) = r0
|
||||
}
|
||||
|
||||
# CHECK: immext(#1024000)
|
||||
# CHECK: memh(##1024056) = r0
|
||||
|
||||
# S2_storerhgp
|
||||
{
|
||||
memh(GP + #56) = r0
|
||||
}
|
||||
|
||||
# CHECK: memh(gp+#56) = r0
|
||||
|
||||
# STriw_abs_V4
|
||||
{
|
||||
memw(##1024056) = r0
|
||||
}
|
||||
|
||||
# CHECK: immext(#1024000)
|
||||
# CHECK: memw(##1024056) = r0
|
||||
|
||||
# S2_storerigp
|
||||
{
|
||||
memw(GP + #56) = r0
|
||||
}
|
||||
|
||||
# CHECK: memw(gp+#56) = r0
|
||||
|
||||
# STrib_abs_nv_V4
|
||||
{
|
||||
r0 = #1
|
||||
memb(##1024056) = r0.new
|
||||
}
|
||||
|
||||
# CHECK: r0 = #1
|
||||
# CHECK: immext(#1024000)
|
||||
# CHECK: memb(##1024056) = r0.new
|
||||
|
||||
# S2_storerbnewgp
|
||||
{
|
||||
r0 = #1
|
||||
memb(GP + #56) = r0.new
|
||||
}
|
||||
|
||||
# CHECK: r0 = #1
|
||||
# CHECK: memb(gp+#56) = r0.new
|
||||
|
||||
# STrih_abs_nv_V4
|
||||
{
|
||||
r0 = #1
|
||||
memh(##1024056) = r0.new
|
||||
}
|
||||
|
||||
# CHECK: r0 = #1
|
||||
# CHECK: immext(#1024000)
|
||||
# CHECK: memh(##1024056) = r0.new
|
||||
|
||||
# S2_storerhnewgp
|
||||
{
|
||||
r0 = #1
|
||||
memh(GP + #56) = r0.new
|
||||
}
|
||||
|
||||
# CHECK: r0 = #1
|
||||
# CHECK: memh(gp+#56) = r0.new
|
||||
|
||||
# STriw_abs_nv_V4
|
||||
{
|
||||
r0 = #1
|
||||
memw(##1024056) = r0.new
|
||||
}
|
||||
|
||||
# CHECK: r0 = #1
|
||||
# CHECK: immext(#1024000)
|
||||
# CHECK: memw(##1024056) = r0.new
|
||||
|
||||
# S2_storerinewgp
|
||||
{
|
||||
r0 = #1
|
||||
memw(GP + #56) = r0.new
|
||||
}
|
||||
|
||||
# CHECK: r0 = #1
|
||||
# CHECK: memw(gp+#56) = r0.new
|
||||
|
||||
# STrid_abs_V4
|
||||
{
|
||||
memd(##1024056) = r1:0
|
||||
}
|
||||
|
||||
# CHECK: immext(#1024000)
|
||||
# CHECK: memd(##1024056) = r1:0
|
||||
|
||||
# S2_storerdgp
|
||||
{
|
||||
memd(GP + #56) = r1:0
|
||||
}
|
||||
|
||||
# CHECK: memd(gp+#56) = r1:0
|
||||
|
||||
# LDrib_abs_V4
|
||||
{
|
||||
r0 = memb(##1024056)
|
||||
}
|
||||
|
||||
# CHECK: immext(#1024000)
|
||||
# CHECK: r0 = memb(##1024056)
|
||||
|
||||
# LDb_GP_V4
|
||||
{
|
||||
r0 = memb(GP + #56)
|
||||
}
|
||||
|
||||
# CHECK: r0 = memb(gp+#56)
|
||||
|
||||
# LDriub_abs_V4
|
||||
{
|
||||
r0 = memub(##1024056)
|
||||
}
|
||||
|
||||
# CHECK: immext(#1024000)
|
||||
# CHECK: r0 = memub(##1024056)
|
||||
|
||||
# LDub_GP_V4
|
||||
{
|
||||
r0 = memub(GP + #56)
|
||||
}
|
||||
|
||||
# CHECK: r0 = memub(gp+#56)
|
||||
|
||||
# LDrih_abs_V4
|
||||
{
|
||||
r0 = memh(##1024056)
|
||||
}
|
||||
|
||||
# CHECK: immext(#1024000)
|
||||
# CHECK: r0 = memh(##1024056)
|
||||
|
||||
# LDh_GP_V4
|
||||
{
|
||||
r0 = memh(GP + #56)
|
||||
}
|
||||
|
||||
# CHECK: r0 = memh(gp+#56)
|
||||
|
||||
# LDriuh_abs_V4
|
||||
{
|
||||
r0 = memuh(##1024056)
|
||||
}
|
||||
|
||||
# CHECK: immext(#1024000)
|
||||
# CHECK: r0 = memuh(##1024056)
|
||||
|
||||
# LDuh_GP_V4
|
||||
{
|
||||
r0 = memuh(GP + #56)
|
||||
}
|
||||
|
||||
# CHECK: r0 = memuh(gp+#56)
|
||||
|
||||
# LDriw_abs_V4
|
||||
{
|
||||
r0 = memw(##1024056)
|
||||
}
|
||||
|
||||
# CHECK: immext(#1024000)
|
||||
# CHECK: r0 = memw(##1024056)
|
||||
|
||||
# LDw_GP_V4
|
||||
{
|
||||
r0 = memw(GP + #56)
|
||||
}
|
||||
|
||||
# CHECK: r0 = memw(gp+#56)
|
||||
|
||||
# LDrid_abs_V4
|
||||
{
|
||||
r1:0 = memd(##1024056)
|
||||
}
|
||||
|
||||
# CHECK: immext(#1024000)
|
||||
# CHECK: r1:0 = memd(##1024056)
|
||||
|
||||
# LDd_GP_V4
|
||||
{
|
||||
r1:0 = memd(GP + #56)
|
||||
}
|
||||
|
||||
# CHECK: r1:0 = memd(gp+#56)
|
||||
|
||||
@ -1,6 +1,11 @@
|
||||
# RUN: llvm-mc -triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
|
||||
# Hexagon Programmer's Reference Manual 11.5 LD
|
||||
|
||||
# Load doubleword
|
||||
# CHECK: 90 ff d5 3a
|
||||
r17:16 = memd(r21 + r31<<#3)
|
||||
# CHECK: b0 c2 c0 49
|
||||
r17:16 = memd(gp+#168)
|
||||
# CHECK: 02 40 00 00
|
||||
# CHECK-NEXT: 10 c5 c0 49
|
||||
r17:16 = memd(##168)
|
||||
@ -62,7 +67,7 @@ if (!p3) r17:16 = memd(r21++#40)
|
||||
# CHECK: 91 ff 15 3a
|
||||
r17 = memb(r21 + r31<<#3)
|
||||
# CHECK: b1 c2 00 49
|
||||
r17 = memb(#21)
|
||||
r17 = memb(gp+#21)
|
||||
# CHECK: 00 40 00 00
|
||||
# CHECK-NEXT: b1 c2 00 49
|
||||
r17 = memb(##21)
|
||||
@ -140,7 +145,7 @@ r17:16 = memh_fifo(r21 ++ I:circ(m1))
|
||||
# CHECK: 91 ff 55 3a
|
||||
r17 = memh(r21 + r31<<#3)
|
||||
# CHECK: b1 c2 40 49
|
||||
r17 = memh(#42)
|
||||
r17 = memh(gp+#42)
|
||||
# CHECK: 00 40 00 00
|
||||
# CHECK-NEXT: 51 c5 40 49
|
||||
r17 = memh(##42)
|
||||
@ -202,7 +207,7 @@ if (!p3) r17 = memh(r21 + #62)
|
||||
# CHECK: 91 ff 35 3a
|
||||
r17 = memub(r21 + r31<<#3)
|
||||
# CHECK: b1 c2 20 49
|
||||
r17 = memub(#21)
|
||||
r17 = memub(gp+#21)
|
||||
# CHECK: 00 40 00 00
|
||||
# CHECK-NEXT: b1 c2 20 49
|
||||
r17 = memub(##21)
|
||||
@ -264,7 +269,7 @@ if (!p3) r17 = memub(r21++#5)
|
||||
# CHECK: 91 ff 75 3a
|
||||
r17 = memuh(r21 + r31<<#3)
|
||||
# CHECK: b1 c2 60 49
|
||||
r17 = memuh(#42)
|
||||
r17 = memuh(gp+#42)
|
||||
# CHECK: 00 40 00 00
|
||||
# CHECK-NEXT: 51 c5 60 49
|
||||
r17 = memuh(##42)
|
||||
@ -326,7 +331,7 @@ if (!p3) r17 = memuh(r21++#10)
|
||||
# CHECK: 91 ff 95 3a
|
||||
r17 = memw(r21 + r31<<#3)
|
||||
# CHECK: b1 c2 80 49
|
||||
r17 = memw(#84)
|
||||
r17 = memw(gp+#84)
|
||||
# CHECK: 01 40 00 00
|
||||
# CHECK-NEXT: 91 c2 80 49
|
||||
r17 = memw(##84)
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
# CHECK: 1f 40 7f 70
|
||||
# CHECK-NEXT: 11 c2 a0 48
|
||||
{ r31 = r31
|
||||
memb(#17) = r31.new }
|
||||
memb(gp+#17) = r31.new }
|
||||
# CHECK: 1f 40 7f 70
|
||||
# CHECK-NEXT: 15 c2 b1 a1
|
||||
{ r31 = r31
|
||||
@ -105,7 +105,7 @@
|
||||
# CHECK: 1f 40 7f 70
|
||||
# CHECK-NEXT: 15 ca a0 48
|
||||
{ r31 = r31
|
||||
memh(#42) = r31.new }
|
||||
memh(gp+#42) = r31.new }
|
||||
# CHECK: 1f 40 7f 70
|
||||
# CHECK-NEXT: 15 ca b1 a1
|
||||
{ r31 = r31
|
||||
@ -201,7 +201,7 @@
|
||||
# CHECK: 1f 40 7f 70
|
||||
# CHECK-NEXT: 15 d2 a0 48
|
||||
{ r31 = r31
|
||||
memw(#84) = r31.new }
|
||||
memw(gp+#84) = r31.new }
|
||||
# CHECK: 1f 40 7f 70
|
||||
# CHECK-NEXT: 15 d2 b1 a1
|
||||
{ r31 = r31
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
# CHECK: 9e f5 d1 3b
|
||||
memd(r17 + r21<<#3) = r31:30
|
||||
# CHECK: 28 d4 c0 48
|
||||
memd(#320) = r21:20
|
||||
memd(gp+#320) = r21:20
|
||||
# CHECK: 02 40 00 00
|
||||
# CHECK-NEXT: 28 d4 c0 48
|
||||
memd(##168) = r21:20
|
||||
@ -83,7 +83,7 @@ memb(r17 + r21<<#3) = r31
|
||||
# CHECK: 9f ca 11 3c
|
||||
memb(r17+#21)=#31
|
||||
# CHECK: 15 d5 00 48
|
||||
memb(#21) = r21
|
||||
memb(gp+#21) = r21
|
||||
# CHECK: 00 40 00 00
|
||||
# CHECK-NEXT: 15 d5 00 48
|
||||
memb(##21) = r21
|
||||
@ -183,9 +183,9 @@ memh(##42) = r21
|
||||
# CHECK-NEXT: 2a d5 60 48
|
||||
memh(##42) = r21.h
|
||||
# CHECK: 2a d5 40 48
|
||||
memh(#84) = r21
|
||||
memh(gp+#84) = r21
|
||||
# CHECK: 2a d5 60 48
|
||||
memh(#84) = r21.h
|
||||
memh(gp+#84) = r21.h
|
||||
# CHECK: 15 df 51 a1
|
||||
memh(r17+#42) = r31
|
||||
# CHECK: 15 df 71 a1
|
||||
@ -341,7 +341,7 @@ memw(r17 + r21<<#3) = r31
|
||||
# CHECK: 9f ca 51 3c
|
||||
memw(r17+#84)=#31
|
||||
# CHECK: 15 df 80 48
|
||||
memw(#84) = r31
|
||||
memw(gp+#84) = r31
|
||||
# CHECK: 01 40 00 00
|
||||
# CHECK-NEXT: 14 d5 80 48
|
||||
memw(##84) = r21
|
||||
|
||||
33
test/MC/Hexagon/load-GPRel.s
Normal file
33
test/MC/Hexagon/load-GPRel.s
Normal file
@ -0,0 +1,33 @@
|
||||
#RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
|
||||
|
||||
# Check encoding bits for GP-relative loads.
|
||||
|
||||
#CHECK: 4fc6ff8c { r13:12 = memd(gp+#421856) }
|
||||
r13:12 = memd(gp+#421856)
|
||||
#CHECK: 4fc6ff8c { r13:12 = memd(gp+#421856) }
|
||||
r13:12 = memd(#421856)
|
||||
|
||||
#CHECK: 4d1ac4d2 { r18 = memb(gp+#46118) }
|
||||
r18 = memb(gp+#46118)
|
||||
#CHECK: 4d1ac4d2 { r18 = memb(gp+#46118) }
|
||||
r18 = memb(#46118)
|
||||
|
||||
#CHECK: 4d81f772 { r18 = memw(gp+#134892) }
|
||||
r18 = memw(gp+#134892)
|
||||
#CHECK: 4d81f772 { r18 = memw(gp+#134892) }
|
||||
r18 = memw(#134892)
|
||||
|
||||
#CHECK: 497de287 { r7 = memuh(gp+#30248) }
|
||||
r7 = memuh(gp+#30248)
|
||||
#CHECK: 497de287 { r7 = memuh(gp+#30248) }
|
||||
r7 = memuh(#30248)
|
||||
|
||||
#CHECK: 4b43e87a { r26 = memh(gp+#36486) }
|
||||
r26 = memh(gp+#36486)
|
||||
#CHECK: 4b43e87a { r26 = memh(gp+#36486) }
|
||||
r26 = memh(#36486)
|
||||
|
||||
#CHECK: 4f37d07f { r31 = memub(gp+#61059) }
|
||||
r31 = memub(gp+#61059)
|
||||
#CHECK: 4f37d07f { r31 = memub(gp+#61059) }
|
||||
r31 = memub(#61059)
|
||||
60
test/MC/Hexagon/parse-pound-hi.s
Normal file
60
test/MC/Hexagon/parse-pound-hi.s
Normal file
@ -0,0 +1,60 @@
|
||||
# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
|
||||
|
||||
memw(gp+#hi_htc_version) = r3
|
||||
#CHECK: 4880c300 { memw(gp+#0) = r3 }
|
||||
memw(gp+#HI) = r3
|
||||
#CHECK: 4880c300 { memw(gp+#0) = r3 }
|
||||
r3 = memw(gp+#HI)
|
||||
#CHECK: 4980c003 { r3 = memw(gp+#0) }
|
||||
memw(gp+#HI_x) = r3
|
||||
#CHECK: 4880c300 { memw(gp+#0) = r3 }
|
||||
r3 = memw(gp+#HI_x)
|
||||
#CHECK: 4980c003 { r3 = memw(gp+#0) }
|
||||
memw(gp+#hi) = r3
|
||||
#CHECK: 4880c300 { memw(gp+#0) = r3 }
|
||||
r3 = memw(gp+#hi)
|
||||
#CHECK: 4980c003 { r3 = memw(gp+#0) }
|
||||
memw(gp+#hi_x) = r3
|
||||
#CHECK: 4880c300 { memw(gp+#0) = r3 }
|
||||
r3 = memw(gp+#hi_x)
|
||||
#CHECK: 4980c003 { r3 = memw(gp+#0) }
|
||||
memw(gp+#lo) = r3
|
||||
#CHECK: 4880c300 { memw(gp+#0) = r3 }
|
||||
r3 = memw(gp+#lo)
|
||||
#CHECK: 4980c003 { r3 = memw(gp+#0) }
|
||||
memw(gp+#lo_x) = r3
|
||||
#CHECK: 4880c300 { memw(gp+#0) = r3 }
|
||||
r3 = memw(gp+#lo_x)
|
||||
#CHECK: 4980c003 { r3 = memw(gp+#0) }
|
||||
memw(gp+#LO) = r3
|
||||
#CHECK: 4880c300 { memw(gp+#0) = r3 }
|
||||
r3 = memw(gp+#lo)
|
||||
#CHECK: 4980c003 { r3 = memw(gp+#0) }
|
||||
memw(gp+#LO_x) = r3
|
||||
#CHECK: 4880c300 { memw(gp+#0) = r3 }
|
||||
r3 = memw(gp+#LO_x)
|
||||
#CHECK: 4980c003 { r3 = memw(gp+#0) }
|
||||
r16.h = #HI(0x405000)
|
||||
#CHECK: 7230c040 { r16.h = #64 }
|
||||
r16.h = #HI (0x405000)
|
||||
#CHECK: 7230c040 { r16.h = #64 }
|
||||
r16.h = #hi(0x405000)
|
||||
#CHECK: 7230c040 { r16.h = #64 }
|
||||
r16.h = #hi (0x405000)
|
||||
#CHECK: 7230c040 { r16.h = #64 }
|
||||
r16.l = #LO(0x405020)
|
||||
#CHECK: 7170d020 { r16.l = #20512 }
|
||||
r16.l = #LO (0x405020)
|
||||
#CHECK: 7170d020 { r16.l = #20512 }
|
||||
r16.l = #lo(0x405020)
|
||||
#CHECK: 7170d020 { r16.l = #20512 }
|
||||
r16.l = #lo (0x405020)
|
||||
#CHECK: 7170d020 { r16.l = #20512 }
|
||||
|
||||
{
|
||||
r19.h = #HI(-559030611)
|
||||
memw(r17+#0) = r19.new
|
||||
}
|
||||
# CHECK: 72f35ead { r19.h = #57005
|
||||
# CHECK: a1b1d200 memw(r17+#0) = r19.new }
|
||||
|
||||
46
test/MC/Hexagon/store-GPRel.s
Normal file
46
test/MC/Hexagon/store-GPRel.s
Normal file
@ -0,0 +1,46 @@
|
||||
#RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d -r - | FileCheck %s
|
||||
|
||||
# Check encoding bits for gp-rel stores.
|
||||
|
||||
#CHECK: 4ab3f229 memw(gp+#105636) = r12.new
|
||||
{ r12 = add(r0,r19)
|
||||
memw(gp+#105636) = r12.new }
|
||||
|
||||
#CHECK: 4ab3f229 memw(gp+#105636) = r12.new
|
||||
{ r12 = add(r0,r19)
|
||||
memw(#105636) = r12.new }
|
||||
|
||||
#CHECK: 4ebdca35 memh(gp+#128106) = r6.new
|
||||
{ r6 = add(r18,r13)
|
||||
memh(gp+#128106) = r6.new }
|
||||
|
||||
#CHECK: 4ebdca35 memh(gp+#128106) = r6.new
|
||||
{ r6 = add(r18,r13)
|
||||
memh(#128106) = r6.new }
|
||||
|
||||
#CHECK: 4eb3e2fc memb(gp+#59388) = r17.new
|
||||
{ r17 = add(r26,r18)
|
||||
memb(gp+#59388) = r17.new }
|
||||
#CHECK: 4eb3e2fc memb(gp+#59388) = r17.new
|
||||
{ r17 = add(r26,r18)
|
||||
memb(#59388) = r17.new }
|
||||
|
||||
#CHECK: 4ad2ea01 { memd(gp+#206856) = r11:10
|
||||
{ memd(gp+#206856) = r11:10 }
|
||||
#CHECK: 4ad2ea01 { memd(gp+#206856) = r11:10
|
||||
{ memd(#206856) = r11:10 }
|
||||
|
||||
#CHECK: 4c9dfa1e { memw(gp+#191608) = r26
|
||||
{ memw(gp+#191608) = r26 }
|
||||
#CHECK: 4c9dfa1e { memw(gp+#191608) = r26
|
||||
{ memw(#191608) = r26 }
|
||||
|
||||
#CHECK: 4855cfdc { memh(gp+#21944) = r15
|
||||
{ memh(gp+#21944) = r15 }
|
||||
#CHECK: 4855cfdc { memh(gp+#21944) = r15
|
||||
{ memh(#21944) = r15 }
|
||||
|
||||
#CHECK: 4a00cea2 { memb(gp+#16546) = r14
|
||||
{ memb(gp+#16546) = r14 }
|
||||
#CHECK: 4a00cea2 { memb(gp+#16546) = r14
|
||||
{ memb(#16546) = r14 }
|
||||
135
test/MC/Hexagon/two-extenders.s
Normal file
135
test/MC/Hexagon/two-extenders.s
Normal file
@ -0,0 +1,135 @@
|
||||
# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
|
||||
#
|
||||
|
||||
# In packets with two extensions assembler is not extending both instructions
|
||||
#
|
||||
|
||||
//['D_DUMMY,C4_or_or,L4_ploadrbtnew_abs,S2_storerfgp']
|
||||
{
|
||||
if (p3) r23 = memb(##2164335510)
|
||||
memh(##1696682668) = r28.h
|
||||
}
|
||||
# CHECK: { immext(#2164335488)
|
||||
# CHECK: if (p3) r23 = memb(##2164335510)
|
||||
# CHECK: immext(#1696682624)
|
||||
# CHECK: memh(##1696682668) = r28.h }
|
||||
|
||||
//['D_DUMMY,C4_or_or,L4_ploadrbtnew_abs,S2_storerfgp']
|
||||
{
|
||||
if (p3.new) r23 = memb(##2164335510)
|
||||
p3 = or(p2,or(p3, p0))
|
||||
}
|
||||
# CHECK: { p3 = or(p2, or(p3, p0))
|
||||
# CHECK: immext(#2164335488)
|
||||
# CHECK: if (p3.new) r23 = memb(##2164335510) }
|
||||
|
||||
|
||||
# -------------------------- Non-extended cases:
|
||||
# -------------------------- Use GP and non GP notation
|
||||
|
||||
R2 = memb(gp+#0x1000)
|
||||
# CHECK: { r2 = memb(gp+#4096) }
|
||||
|
||||
R3 = memh(gp+#0x1000)
|
||||
# CHECK: { r3 = memh(gp+#4096) }
|
||||
|
||||
r4 = memub(gp+#0x1000)
|
||||
# CHECK: { r4 = memub(gp+#4096) }
|
||||
|
||||
r5 = memuh(gp+#0x1000)
|
||||
# CHECK: { r5 = memuh(gp+#4096) }
|
||||
|
||||
r6 = memw(gp+#0x1000)
|
||||
# CHECK: { r6 = memw(gp+#4096) }
|
||||
|
||||
R1:0 = memd(gp+#0x1000)
|
||||
# CHECK: { r1:0 = memd(gp+#4096) }
|
||||
|
||||
{R25 = #1; memb(gp+#0x1000) = R25.new}
|
||||
# CHECK: { r25 = #1
|
||||
# CHECK-NEXT: memb(gp+#4096) = r25.new }
|
||||
|
||||
{R26 = #1; memh(gp+#0x1000) = R26.new}
|
||||
# CHECK: { r26 = #1
|
||||
# CHECK-NEXT: memh(gp+#4096) = r26.new }
|
||||
|
||||
{R27 = #1; memw(gp+#0x1000) = R27.new}
|
||||
# CHECK: { r27 = #1
|
||||
# CHECK-NEXT: memw(gp+#4096) = r27.new }
|
||||
|
||||
memd(gp+#0x1000) = R1:0
|
||||
# CHECK: { memd(gp+#4096) = r1:0 }
|
||||
|
||||
memb(gp+#0x1000) = R2
|
||||
# CHECK: { memb(gp+#4096) = r2 }
|
||||
|
||||
memh(gp+#0x1000) = r3.h
|
||||
# CHECK: { memh(gp+#4096) = r3.h }
|
||||
|
||||
memh(gp+#0x1000) = R4
|
||||
# CHECK: { memh(gp+#4096) = r4 }
|
||||
|
||||
memw(gp+#0x1000) = R5
|
||||
# CHECK: { memw(gp+#4096) = r5 }
|
||||
|
||||
# -------------------------- Extended cases:
|
||||
# -------------------------- Use GP and non GP notation
|
||||
|
||||
R11:10 = memd(##0x1000)
|
||||
# CHECK: { immext(#4096)
|
||||
# CHECK-NEXT: r11:10 = memd(##4096) }
|
||||
|
||||
R11 = memb(##0x1000)
|
||||
# CHECK: { immext(#4096)
|
||||
# CHECK-NEXT: r11 = memb(##4096) }
|
||||
|
||||
R12 = memh(##0x1000)
|
||||
# CHECK: { immext(#4096)
|
||||
# CHECK-NEXT: r12 = memh(##4096) }
|
||||
|
||||
r13 = memub(##0x1000)
|
||||
# CHECK: { immext(#4096)
|
||||
# CHECK-NEXT: r13 = memub(##4096) }
|
||||
|
||||
r14 = memuh(##0x1000)
|
||||
# CHECK: { immext(#4096)
|
||||
# CHECK-NEXT: r14 = memuh(##4096) }
|
||||
|
||||
r15 = memw(##0x1000)
|
||||
# CHECK: { immext(#4096)
|
||||
# CHECK-NEXT: r15 = memw(##4096) }
|
||||
|
||||
{R22 = #1; memb(##0x1000) = R22.new}
|
||||
# CHECK: { r22 = #1
|
||||
# CHECK-NEXT: immext(#4096)
|
||||
# CHECK-NEXT: memb(##4096) = r22.new }
|
||||
|
||||
{R23 = #1; memh(##0x1000) = R23.new}
|
||||
# CHECK: { r23 = #1
|
||||
# CHECK-NEXT: immext(#4096)
|
||||
# CHECK-NEXT: memh(##4096) = r23.new }
|
||||
|
||||
{R24 = #1; memw(##0x1000) = R24.new}
|
||||
# CHECK: { r24 = #1
|
||||
# CHECK-NEXT: immext(#4096)
|
||||
# CHECK-NEXT: memw(##4096) = r24.new }
|
||||
|
||||
memd(##0x1000) = R17:16
|
||||
# CHECK: { immext(#4096)
|
||||
# CHECK-NEXT: memd(##4096) = r17:16 }
|
||||
|
||||
memb(##0x1000) = R18
|
||||
# CHECK: { immext(#4096)
|
||||
# CHECK-NEXT: memb(##4096) = r18 }
|
||||
|
||||
memh(##0x1000) = r19.h
|
||||
# CHECK: { immext(#4096)
|
||||
# CHECK-NEXT: memh(##4096) = r19.h }
|
||||
|
||||
memh(##0x1000) = R20
|
||||
# CHECK: { immext(#4096)
|
||||
# CHECK-NEXT: memh(##4096) = r20 }
|
||||
|
||||
memw(##0x1000) = R21
|
||||
# CHECK: { immext(#4096)
|
||||
# CHECK-NEXT: memw(##4096) = r21 }
|
||||
Loading…
Reference in New Issue
Block a user