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[Hexagon] Properly handle 'q' constraint in 128-byte vector mode

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296772 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2017-03-02 17:50:24 +00:00
parent 6981f9a951
commit 3f339ad775
2 changed files with 25 additions and 22 deletions
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32
lib/Target/Hexagon/HexagonISelLowering.cpp
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@ -3057,37 +3057,25 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(
return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
}
case 'q': // q0-q3
switch (VT.SimpleTy) {
switch (VT.getSizeInBits()) {
default:
llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
case MVT::v1024i1:
case MVT::v512i1:
case MVT::v32i16:
case MVT::v16i32:
case MVT::v64i8:
case MVT::v8i64:
llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size");
case 512:
return std::make_pair(0U, &Hexagon::VecPredRegsRegClass);
case 1024:
return std::make_pair(0U, &Hexagon::VecPredRegs128BRegClass);
}
case 'v': // V0-V31
switch (VT.SimpleTy) {
switch (VT.getSizeInBits()) {
default:
llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
case MVT::v16i32:
case MVT::v32i16:
case MVT::v64i8:
case MVT::v8i64:
llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size");
case 512:
return std::make_pair(0U, &Hexagon::VectorRegsRegClass);
case MVT::v32i32:
case MVT::v64i16:
case MVT::v16i64:
case MVT::v128i8:
case 1024:
if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl)
return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass);
return std::make_pair(0U, &Hexagon::VecDblRegsRegClass);
case MVT::v256i8:
case MVT::v128i16:
case MVT::v64i32:
case MVT::v32i64:
case 2048:
return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass);
}

15
test/CodeGen/Hexagon/inline-asm-vecpred128.ll Normal file
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@ -0,0 +1,15 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; REQUIRES: asserts
; Make sure we can handle the 'q' constraint in the 128-byte mode.
target triple = "hexagon"
; CHECK-LABEL: fred
; CHECK: if (q{{[0-3]}}) vmem
define void @fred() #0 {
tail call void asm sideeffect "if ($0) vmem($1) = $2;", "q,r,v,~{memory}"(<32 x i32> undef, <32 x i32>* undef, <32 x i32> undef) #0
ret void
}
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }