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[DAGCombiner] Add another combine from build vector to shuffle
Add support for combining a build vector to a shuffle. When the build vector is of extracted elements from 2 vectors (vec1, vec2) where vec2 is 2 times smaller than vec1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305883 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -14055,6 +14055,11 @@ SDValue DAGCombiner::createBuildVecShuffle(const SDLoc &DL, SDNode *N,
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// when we start sorting the vectors by type.
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return SDValue();
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}
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} else if (InVT2.getSizeInBits() * 2 == VT.getSizeInBits() &&
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InVT1.getSizeInBits() == VT.getSizeInBits()) {
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SmallVector<SDValue, 2> ConcatOps(2, DAG.getUNDEF(InVT2));
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ConcatOps[0] = VecIn2;
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VecIn2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps);
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} else {
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// TODO: Support cases where the length mismatch isn't exactly by a
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// factor of 2.
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@ -1378,7 +1378,7 @@ entry:
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define <2 x i64> @test_concat_v2i64_v2i64_v1i64(<2 x i64> %x, <1 x i64> %y) #0 {
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; CHECK-LABEL: test_concat_v2i64_v2i64_v1i64:
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; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
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; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
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entry:
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%vecext = extractelement <2 x i64> %x, i32 0
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%vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
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@ -3,42 +3,18 @@
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define <32 x i8> @foo(<48 x i8>* %x0, <16 x i32> %x1, <16 x i32> %x2) {
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; CHECK-LABEL: foo:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovdqu 32(%rdi), %xmm0
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; CHECK-NEXT: vmovdqu (%rdi), %ymm1
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; CHECK-NEXT: vextracti128 $1, %ymm1, %xmm2
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; CHECK-NEXT: vpextrb $0, %xmm2, %eax
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; CHECK-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,3,4,6,7,9,10,12,13,15],zero,zero,zero,zero,zero
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; CHECK-NEXT: vpinsrb $11, %eax, %xmm1, %xmm1
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; CHECK-NEXT: vpextrb $2, %xmm2, %eax
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; CHECK-NEXT: vpinsrb $12, %eax, %xmm1, %xmm1
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; CHECK-NEXT: vpextrb $3, %xmm2, %eax
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; CHECK-NEXT: vpinsrb $13, %eax, %xmm1, %xmm1
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; CHECK-NEXT: vpextrb $5, %xmm2, %eax
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; CHECK-NEXT: vpinsrb $14, %eax, %xmm1, %xmm1
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; CHECK-NEXT: vpextrb $6, %xmm2, %eax
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; CHECK-NEXT: vpinsrb $15, %eax, %xmm1, %xmm1
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; CHECK-NEXT: vpextrb $1, %xmm0, %eax
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; CHECK-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[8,9,11,12,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; CHECK-NEXT: vpinsrb $6, %eax, %xmm2, %xmm2
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; CHECK-NEXT: vpextrb $2, %xmm0, %eax
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; CHECK-NEXT: vpinsrb $7, %eax, %xmm2, %xmm2
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; CHECK-NEXT: vpextrb $4, %xmm0, %eax
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; CHECK-NEXT: vpinsrb $8, %eax, %xmm2, %xmm2
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; CHECK-NEXT: vpextrb $5, %xmm0, %eax
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; CHECK-NEXT: vpinsrb $9, %eax, %xmm2, %xmm2
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; CHECK-NEXT: vpextrb $7, %xmm0, %eax
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; CHECK-NEXT: vpinsrb $10, %eax, %xmm2, %xmm2
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; CHECK-NEXT: vpextrb $8, %xmm0, %eax
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; CHECK-NEXT: vpinsrb $11, %eax, %xmm2, %xmm2
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; CHECK-NEXT: vpextrb $10, %xmm0, %eax
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; CHECK-NEXT: vpinsrb $12, %eax, %xmm2, %xmm2
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; CHECK-NEXT: vpextrb $11, %xmm0, %eax
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; CHECK-NEXT: vpinsrb $13, %eax, %xmm2, %xmm2
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; CHECK-NEXT: vpextrb $13, %xmm0, %eax
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; CHECK-NEXT: vpinsrb $14, %eax, %xmm2, %xmm2
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; CHECK-NEXT: vpextrb $14, %xmm0, %eax
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; CHECK-NEXT: vpinsrb $15, %eax, %xmm2, %xmm0
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; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
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; CHECK-NEXT: vmovdqu (%rdi), %ymm0
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; CHECK-NEXT: vmovdqu 32(%rdi), %xmm1
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; CHECK-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[u,u,u,u,u,u,1,2,4,5,7,8,10,11,13,14]
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; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm1
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; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm2
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; CHECK-NEXT: vpshufb {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,2,3,5,6]
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; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,3,4,6,7,9,10,12,13,15],zero,zero,zero,zero,zero
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; CHECK-NEXT: vpor %xmm3, %xmm0, %xmm0
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; CHECK-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[8,9,11,12,14,15,u,u,u,u,u,u,u,u,u,u]
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; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
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; CHECK-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0,0,0,0,0,0]
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; CHECK-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = load <48 x i8>, <48 x i8>* %x0, align 1
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%2 = shufflevector <48 x i8> %1, <48 x i8> undef, <32 x i32> <i32 0, i32 1, i32 3, i32 4, i32 6, i32 7, i32 9, i32 10, i32 12, i32 13, i32 15, i32 16, i32 18, i32 19, i32 21, i32 22, i32 24, i32 25, i32 27, i32 28, i32 30, i32 31, i32 33, i32 34, i32 36, i32 37, i32 39, i32 40, i32 42, i32 43, i32 45, i32 46>
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