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The new t2LEApcrel* pseudo instructions need the size specified.
rdar://8768390 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121876 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -266,6 +266,13 @@ class tPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
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list<Predicate> Predicates = [IsThumb];
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}
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// PseudoInst that's Thumb2-mode only.
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class t2PseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
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list<dag> pattern>
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: PseudoInst<oops, iops, itin, pattern> {
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let SZ = sz;
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list<Predicate> Predicates = [IsThumb2];
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}
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// Almost all ARM instructions are predicable.
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class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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IndexMode im, Format f, InstrItinClass itin,
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@ -1156,11 +1156,12 @@ def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
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}
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let neverHasSideEffects = 1, isReMaterializable = 1 in
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def t2LEApcrel : PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
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IIC_iALUi, []>;
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def t2LEApcrelJT : PseudoInst<(outs rGPR:$Rd),
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(ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
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[]>;
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def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
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Size4Bytes, IIC_iALUi, []>;
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def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
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(ins i32imm:$label, nohash_imm:$id, pred:$p),
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Size4Bytes, IIC_iALUi,
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[]>;
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// FIXME: None of these add/sub SP special instructions should be necessary
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