RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-11 05:35:11 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Implement shift-simplify.ll:test[45].

Browse Source 
First teach instcombine that sign bit checks only demand the 
sign bit, this allows simplify demanded bits to hack on 
expressions better.

Second, teach instcombine that ashr is useless if only the
sign bit is demanded.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39880 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-07-15 20:54:51 +00:00
parent a0141b90a3
commit 4241e4da85
2 changed files with 35 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
lib/Transforms/Scalar/InstructionCombining.cpp
View File

@ -1342,6 +1342,11 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask,
InsertNewInstBefore(cast<Instruction>(NewVal), *I);
return UpdateValueUsesWith(I, NewVal);
}
// If the sign bit is the only bit demanded by this ashr, then there is no
// need to do it, the shift doesn't change the high bit.
if (DemandedMask.isSignBit())
return UpdateValueUsesWith(I, I->getOperand(0));
if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
uint32_t ShiftAmt = SA->getLimitedValue(BitWidth);
@ -4841,22 +4846,29 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) {
// already been handled above, this requires little checking.
//
switch (I.getPredicate()) {
default: break;
case ICmpInst::ICMP_ULE:
return new ICmpInst(ICmpInst::ICMP_ULT, Op0, AddOne(CI));
case ICmpInst::ICMP_SLE:
return new ICmpInst(ICmpInst::ICMP_SLT, Op0, AddOne(CI));
case ICmpInst::ICMP_UGE:
return new ICmpInst( ICmpInst::ICMP_UGT, Op0, SubOne(CI));
case ICmpInst::ICMP_SGE:
return new ICmpInst(ICmpInst::ICMP_SGT, Op0, SubOne(CI));
default: break;
case ICmpInst::ICMP_ULE:
return new ICmpInst(ICmpInst::ICMP_ULT, Op0, AddOne(CI));
case ICmpInst::ICMP_SLE:
return new ICmpInst(ICmpInst::ICMP_SLT, Op0, AddOne(CI));
case ICmpInst::ICMP_UGE:
return new ICmpInst( ICmpInst::ICMP_UGT, Op0, SubOne(CI));
case ICmpInst::ICMP_SGE:
return new ICmpInst(ICmpInst::ICMP_SGT, Op0, SubOne(CI));
}
// See if we can fold the comparison based on bits known to be zero or one
// in the input.
// in the input. If this comparison is a normal comparison, it demands all
// bits, if it is a sign bit comparison, it only demands the sign bit.
bool UnusedBit;
bool isSignBit = isSignBitCheck(I.getPredicate(), CI, UnusedBit);
uint32_t BitWidth = cast<IntegerType>(Ty)->getBitWidth();
APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
if (SimplifyDemandedBits(Op0, APInt::getAllOnesValue(BitWidth),
if (SimplifyDemandedBits(Op0,
isSignBit ? APInt::getSignBit(BitWidth)
: APInt::getAllOnesValue(BitWidth),
KnownZero, KnownOne, 0))
return &I;

12
test/Transforms/InstCombine/shift-simplify.ll
View File

@ -28,3 +28,15 @@ define i1 @test3(i32 %X) {
ret i1 %tmp2
}
define i1 @test4(i32 %X) {
%tmp1 = lshr i32 %X, 7
%tmp2 = icmp slt i32 %tmp1, 0
ret i1 %tmp2
}
define i1 @test5(i32 %X) {
%tmp1 = ashr i32 %X, 7
%tmp2 = icmp slt i32 %tmp1, 0
ret i1 %tmp2
}