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misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for external users of TargetSchedule.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165564 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-10-09 23:44:26 +00:00
parent 714973e459
commit 42bb106118
2 changed files with 14 additions and 8 deletions
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4
include/llvm/CodeGen/TargetSchedule.h
View File

@ -45,11 +45,11 @@ public:
/// Return true if this machine model includes an instruction-level scheduling
/// model. This is more detailed than the course grain IssueWidth and default
/// latency properties, but separate from the per-cycle itinerary data.
bool hasInstrSchedModel() const { return SchedModel.hasInstrSchedModel(); }
bool hasInstrSchedModel() const;
/// Return true if this machine model includes cycle-to-cycle itinerary
/// data. This models scheduling at each stage in the processor pipeline.
bool hasInstrItineraries() const { return !InstrItins.isEmpty(); }
bool hasInstrItineraries() const;
/// computeOperandLatency - Compute and return the latency of the given data
/// dependent def and use when the operand indices are already known. UseMI

18
lib/CodeGen/TargetSchedule.cpp
View File

@ -27,6 +27,14 @@ static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
cl::desc("Use InstrItineraryData for latency lookup"));
bool TargetSchedModel::hasInstrSchedModel() const {
return EnableSchedModel && SchedModel.hasInstrSchedModel();
}
bool TargetSchedModel::hasInstrItineraries() const {
return EnableSchedItins && !InstrItins.isEmpty();
}
void TargetSchedModel::init(const MCSchedModel &sm,
const TargetSubtargetInfo *sti,
const TargetInstrInfo *tii) {
@ -47,14 +55,12 @@ int TargetSchedModel::getDefLatency(const MachineInstr *DefMI,
if (FindMin) {
// If MinLatency is invalid, then use the itinerary for MinLatency. If no
// itinerary exists either, then use single cycle latency.
if (SchedModel.MinLatency < 0
&& !(EnableSchedItins && hasInstrItineraries())) {
if (SchedModel.MinLatency < 0 && !hasInstrItineraries()) {
return 1;
}
return SchedModel.MinLatency;
}
else if (!(EnableSchedModel && hasInstrSchedModel())
&& !(EnableSchedItins && hasInstrItineraries())) {
else if (!hasInstrSchedModel() && !hasInstrItineraries()) {
return TII->defaultDefLatency(&SchedModel, DefMI);
}
// ...operand lookup required
@ -123,7 +129,7 @@ unsigned TargetSchedModel::computeOperandLatency(
if (DefLatency >= 0)
return DefLatency;
if (EnableSchedItins && hasInstrItineraries()) {
if (hasInstrItineraries()) {
int OperLatency = 0;
if (UseMI) {
OperLatency =
@ -145,7 +151,7 @@ unsigned TargetSchedModel::computeOperandLatency(
TII->defaultDefLatency(&SchedModel, DefMI));
return InstrLatency;
}
assert(!FindMin && EnableSchedModel && hasInstrSchedModel() &&
assert(!FindMin && hasInstrSchedModel() &&
"Expected a SchedModel for this cpu");
const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);