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ARM VST1 w/ writeback assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143369 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
0ba11795ee
commit
4334e03252
@ -273,13 +273,17 @@ static const NEONLdStTableEntry NEONLdStTable[] = {
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{ ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, true, SingleSpc, 3, 1 ,true},
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{ ARM::VST1q16Pseudo, ARM::VST1q16, false, false, false, SingleSpc, 2, 4 ,true},
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{ ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
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{ ARM::VST1q16PseudoWB_fixed, ARM::VST1q16wb_fixed, false, true, false, SingleSpc, 2, 4 ,false},
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{ ARM::VST1q16PseudoWB_register, ARM::VST1q16wb_register, false, true, true, SingleSpc, 2, 4 ,false},
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{ ARM::VST1q32Pseudo, ARM::VST1q32, false, false, false, SingleSpc, 2, 2 ,true},
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{ ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
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{ ARM::VST1q32PseudoWB_fixed, ARM::VST1q32wb_fixed, false, true, false, SingleSpc, 2, 2 ,false},
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{ ARM::VST1q32PseudoWB_register, ARM::VST1q32wb_register, false, true, true, SingleSpc, 2, 2 ,false},
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{ ARM::VST1q64Pseudo, ARM::VST1q64, false, false, false, SingleSpc, 2, 1 ,true},
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{ ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, true, SingleSpc, 2, 1 ,true},
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{ ARM::VST1q64PseudoWB_fixed, ARM::VST1q64wb_fixed, false, true, false, SingleSpc, 2, 1 ,false},
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{ ARM::VST1q64PseudoWB_register, ARM::VST1q64wb_register, false, true, true, SingleSpc, 2, 1 ,false},
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{ ARM::VST1q8Pseudo, ARM::VST1q8, false, false, false, SingleSpc, 2, 8 ,true},
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{ ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
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{ ARM::VST1q8PseudoWB_fixed, ARM::VST1q8wb_fixed, false, true, false, SingleSpc, 2, 8 ,false},
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{ ARM::VST1q8PseudoWB_register, ARM::VST1q8wb_register, false, true, true, SingleSpc, 2, 8 ,false},
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{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
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{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
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@ -504,10 +508,12 @@ void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
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unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
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unsigned D0, D1, D2, D3;
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GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
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MIB.addReg(D0).addReg(D1);
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if (NumRegs > 2)
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MIB.addReg(D0);
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if (NumRegs > 1 && TableEntry->copyAllListRegs)
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MIB.addReg(D1);
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if (NumRegs > 2 && TableEntry->copyAllListRegs)
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MIB.addReg(D2);
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if (NumRegs > 3)
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if (NumRegs > 3 && TableEntry->copyAllListRegs)
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MIB.addReg(D3);
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// Copy the predicate operands.
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@ -1153,10 +1159,14 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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case ARM::VST1q16Pseudo:
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case ARM::VST1q32Pseudo:
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case ARM::VST1q64Pseudo:
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case ARM::VST1q8Pseudo_UPD:
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case ARM::VST1q16Pseudo_UPD:
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case ARM::VST1q32Pseudo_UPD:
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case ARM::VST1q64Pseudo_UPD:
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case ARM::VST1q8PseudoWB_fixed:
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case ARM::VST1q16PseudoWB_fixed:
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case ARM::VST1q32PseudoWB_fixed:
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case ARM::VST1q64PseudoWB_fixed:
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case ARM::VST1q8PseudoWB_register:
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case ARM::VST1q16PseudoWB_register:
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case ARM::VST1q32PseudoWB_register:
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case ARM::VST1q64PseudoWB_register:
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case ARM::VST2d8Pseudo:
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case ARM::VST2d16Pseudo:
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case ARM::VST2d32Pseudo:
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@ -1566,6 +1566,19 @@ static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
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case ARM::VLD1q16PseudoWB_fixed: return ARM::VLD1q16PseudoWB_register;
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case ARM::VLD1q32PseudoWB_fixed: return ARM::VLD1q32PseudoWB_register;
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case ARM::VLD1q64PseudoWB_fixed: return ARM::VLD1q64PseudoWB_register;
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case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
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case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
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case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
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case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
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case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
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case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
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case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
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case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
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case ARM::VST1q8PseudoWB_fixed: return ARM::VST1q8PseudoWB_register;
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case ARM::VST1q16PseudoWB_fixed: return ARM::VST1q16PseudoWB_register;
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case ARM::VST1q32PseudoWB_fixed: return ARM::VST1q32PseudoWB_register;
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case ARM::VST1q64PseudoWB_fixed: return ARM::VST1q64PseudoWB_register;
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}
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return Opc; // If not one we handle, return it unchanged.
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}
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@ -1635,11 +1648,12 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
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SDValue Inc = N->getOperand(AddrOpIdx + 1);
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// FIXME: VLD1 fixed increment doesn't need Reg0. Remove the reg0
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// case entirely when the rest are updated to that form, too.
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// Do that before committing this change. Likewise, the opcode
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// update call will become unconditional.
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if (NumVecs == 1 && !isa<ConstantSDNode>(Inc.getNode()))
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Opc = getVLDSTRegisterUpdateOpcode(Opc);
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if (NumVecs != 1 || !isa<ConstantSDNode>(Inc.getNode()))
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// We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
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// check for that explicitly too. Horribly hacky, but temporary.
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if ((NumVecs != 1 && Opc != ARM::VLD1q64PseudoWB_fixed) ||
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!isa<ConstantSDNode>(Inc.getNode()))
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Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
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}
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Ops.push_back(Pred);
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@ -1782,7 +1796,15 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
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Ops.push_back(Align);
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if (isUpdating) {
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SDValue Inc = N->getOperand(AddrOpIdx + 1);
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Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
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// FIXME: VST1 fixed increment doesn't need Reg0. Remove the reg0
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// case entirely when the rest are updated to that form, too.
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if (NumVecs == 1 && !isa<ConstantSDNode>(Inc.getNode()))
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Opc = getVLDSTRegisterUpdateOpcode(Opc);
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// We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
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// check for that explicitly too. Horribly hacky, but temporary.
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if ((NumVecs != 1 && Opc != ARM::VST1q64PseudoWB_fixed) ||
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!isa<ConstantSDNode>(Inc.getNode()))
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Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
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}
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Ops.push_back(SrcReg);
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Ops.push_back(Pred);
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@ -2844,16 +2866,18 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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}
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case ARMISD::VST1_UPD: {
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unsigned DOpcodes[] = { ARM::VST1d8_UPD, ARM::VST1d16_UPD,
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ARM::VST1d32_UPD, ARM::VST1d64_UPD };
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unsigned QOpcodes[] = { ARM::VST1q8Pseudo_UPD, ARM::VST1q16Pseudo_UPD,
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ARM::VST1q32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
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unsigned DOpcodes[] = { ARM::VST1d8wb_fixed, ARM::VST1d16wb_fixed,
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ARM::VST1d32wb_fixed, ARM::VST1d64wb_fixed };
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unsigned QOpcodes[] = { ARM::VST1q8PseudoWB_fixed,
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ARM::VST1q16PseudoWB_fixed,
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ARM::VST1q32PseudoWB_fixed,
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ARM::VST1q64PseudoWB_fixed };
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return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
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}
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case ARMISD::VST2_UPD: {
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unsigned DOpcodes[] = { ARM::VST2d8Pseudo_UPD, ARM::VST2d16Pseudo_UPD,
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ARM::VST2d32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
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ARM::VST2d32Pseudo_UPD, ARM::VST1q64PseudoWB_fixed};
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unsigned QOpcodes[] = { ARM::VST2q8Pseudo_UPD, ARM::VST2q16Pseudo_UPD,
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ARM::VST2q32Pseudo_UPD };
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return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
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@ -1208,6 +1208,14 @@ class VSTQWBPseudo<InstrItinClass itin>
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: PseudoNLdSt<(outs GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
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"$addr.addr = $wb">;
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class VSTQWBfixedPseudo<InstrItinClass itin>
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: PseudoNLdSt<(outs GPR:$wb),
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(ins addrmode6:$addr, QPR:$src), itin,
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"$addr.addr = $wb">;
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class VSTQWBregisterPseudo<InstrItinClass itin>
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: PseudoNLdSt<(outs GPR:$wb),
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(ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
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"$addr.addr = $wb">;
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class VSTQQPseudo<InstrItinClass itin>
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: PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
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class VSTQQWBPseudo<InstrItinClass itin>
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@ -1254,36 +1262,65 @@ def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
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def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
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// ...with address register writeback:
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class VST1DWB<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
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"vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVSTInstruction";
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multiclass VST1DWB<bits<4> op7_4, string Dt> {
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def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
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"vst1", Dt, "$Vd, $Rn!",
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"$Rn.addr = $wb", []> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVSTInstruction";
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let AsmMatchConverter = "cvtVSTwbFixed";
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}
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def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
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IIC_VLD1u,
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"vst1", Dt, "$Vd, $Rn, $Rm",
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"$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVSTInstruction";
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let AsmMatchConverter = "cvtVSTwbRegister";
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}
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}
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class VST1QWB<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
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IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVSTInstruction";
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multiclass VST1QWB<bits<4> op7_4, string Dt> {
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def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, VecListTwoD:$Vd), IIC_VLD1x2u,
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"vst1", Dt, "$Vd, $Rn!",
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"$Rn.addr = $wb", []> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVSTInstruction";
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let AsmMatchConverter = "cvtVSTwbFixed";
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}
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def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm, VecListTwoD:$Vd),
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IIC_VLD1x2u,
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"vst1", Dt, "$Vd, $Rn, $Rm",
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVSTInstruction";
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let AsmMatchConverter = "cvtVSTwbRegister";
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}
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}
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def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
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def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
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def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
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def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
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defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
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defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
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defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
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defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
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def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
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def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
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def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
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def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
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defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
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defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
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defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
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defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
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def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
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def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
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def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
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def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
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def VST1q8PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
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def VST1q16PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
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def VST1q32PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
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def VST1q64PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
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def VST1q8PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
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def VST1q16PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
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def VST1q32PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
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def VST1q64PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
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// ...with 3 registers
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class VST1D3<bits<4> op7_4, string Dt>
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@ -202,6 +202,10 @@ class ARMAsmParser : public MCTargetAsmParser {
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool validateInstruction(MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
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@ -3429,6 +3433,36 @@ cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
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return true;
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}
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bool ARMAsmParser::
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cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// Create a writeback register dummy placeholder.
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Inst.addOperand(MCOperand::CreateImm(0));
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// Vn
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((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
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// Vt
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((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
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// pred
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((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
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return true;
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}
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bool ARMAsmParser::
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cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// Create a writeback register dummy placeholder.
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Inst.addOperand(MCOperand::CreateImm(0));
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// Vn
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((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
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// Vm
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((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
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// Vt
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((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
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// pred
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((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
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return true;
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}
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/// Parse an ARM memory expression, return false if successful else return true
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/// or an error. The first token must be a '[' when called.
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bool ARMAsmParser::
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@ -2183,14 +2183,22 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
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// Writeback Operand
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switch (Inst.getOpcode()) {
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case ARM::VST1d8_UPD:
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case ARM::VST1d16_UPD:
|
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case ARM::VST1d32_UPD:
|
||||
case ARM::VST1d64_UPD:
|
||||
case ARM::VST1q8_UPD:
|
||||
case ARM::VST1q16_UPD:
|
||||
case ARM::VST1q32_UPD:
|
||||
case ARM::VST1q64_UPD:
|
||||
case ARM::VST1d8wb_fixed:
|
||||
case ARM::VST1d16wb_fixed:
|
||||
case ARM::VST1d32wb_fixed:
|
||||
case ARM::VST1d64wb_fixed:
|
||||
case ARM::VST1d8wb_register:
|
||||
case ARM::VST1d16wb_register:
|
||||
case ARM::VST1d32wb_register:
|
||||
case ARM::VST1d64wb_register:
|
||||
case ARM::VST1q8wb_fixed:
|
||||
case ARM::VST1q16wb_fixed:
|
||||
case ARM::VST1q32wb_fixed:
|
||||
case ARM::VST1q64wb_fixed:
|
||||
case ARM::VST1q8wb_register:
|
||||
case ARM::VST1q16wb_register:
|
||||
case ARM::VST1q32wb_register:
|
||||
case ARM::VST1q64wb_register:
|
||||
case ARM::VST1d8T_UPD:
|
||||
case ARM::VST1d16T_UPD:
|
||||
case ARM::VST1d32T_UPD:
|
||||
@ -2249,10 +2257,6 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
|
||||
case ARM::VST1q16:
|
||||
case ARM::VST1q32:
|
||||
case ARM::VST1q64:
|
||||
case ARM::VST1q8_UPD:
|
||||
case ARM::VST1q16_UPD:
|
||||
case ARM::VST1q32_UPD:
|
||||
case ARM::VST1q64_UPD:
|
||||
case ARM::VST1d8T:
|
||||
case ARM::VST1d16T:
|
||||
case ARM::VST1d32T:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user