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[Thumb] 32-bit encodings of 'cps' are not valid for v7M
v7M only allows the 16-bit encoding of the 'cps' (Change Processor State) instruction, and does not have the 32-bit encoding which is valid from v6T2 onwards. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218382 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3674,7 +3674,8 @@ let isBranch = 1, isTerminator = 1 in {
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// operands, create 3 versions of the same instruction. Once there's a clean
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// framework to represent optional operands, change this behavior.
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class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
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!strconcat("cps", asm_op), []> {
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!strconcat("cps", asm_op), []>,
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Requires<[IsThumb2, IsNotMClass]> {
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bits<2> imod;
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bits<3> iflags;
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bits<5> mode;
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@ -5514,6 +5514,8 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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Operands.push_back(ARMOperand::CreateImm(
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MCConstantExpr::Create(ProcessorIMod, getContext()),
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NameLoc, NameLoc));
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} else if (Mnemonic == "cps" && isMClass()) {
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return Error(NameLoc, "instruction 'cps' requires effect for M-class");
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}
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// Add the remaining tokens in the mnemonic.
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17
test/MC/ARM/cps.s
Normal file
17
test/MC/ARM/cps.s
Normal file
@ -0,0 +1,17 @@
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@ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s | FileCheck %s
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@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
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cpsie f
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cpsie i, #3
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cps #0
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@ CHECK: cpsie f @ encoding: [0x61,0xb6]
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@ CHECK: cpsie i, #3 @ encoding: [0xaf,0xf3,0x43,0x85]
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@ CHECK: cps #0 @ encoding: [0xaf,0xf3,0x00,0x81]
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@ UNDEF-DAG: cpsie f @ encoding: [0x61,0xb6]
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@ UNDEF-DAG: error: instruction requires:
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@ UNDEF-DAG: error: instruction 'cps' requires effect for M-class
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