RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-29 06:30:39 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

eliminate uses of cerr()

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79834 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-08-23 07:05:07 +00:00
parent 893e1c90a0
commit 4437ae213d
16 changed files with 136 additions and 116 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
View File

@ -15,10 +15,11 @@
#include "LegalizeTypes.h"
#include "llvm/CallingConv.h"
#include "llvm/Target/TargetData.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
static cl::opt<bool>
@ -114,42 +115,42 @@ void DAGTypeLegalizer::PerformExpensiveChecks() {
if (I->getNodeId() != Processed) {
if (Mapped != 0) {
cerr << "Unprocessed value in a map!";
errs() << "Unprocessed value in a map!";
Failed = true;
}
} else if (isTypeLegal(Res.getValueType()) || IgnoreNodeResults(I)) {
if (Mapped > 1) {
cerr << "Value with legal type was transformed!";
errs() << "Value with legal type was transformed!";
Failed = true;
}
} else {
if (Mapped == 0) {
cerr << "Processed value not in any map!";
errs() << "Processed value not in any map!";
Failed = true;
} else if (Mapped & (Mapped - 1)) {
cerr << "Value in multiple maps!";
errs() << "Value in multiple maps!";
Failed = true;
}
}
if (Failed) {
if (Mapped & 1)
cerr << " ReplacedValues";
errs() << " ReplacedValues";
if (Mapped & 2)
cerr << " PromotedIntegers";
errs() << " PromotedIntegers";
if (Mapped & 4)
cerr << " SoftenedFloats";
errs() << " SoftenedFloats";
if (Mapped & 8)
cerr << " ScalarizedVectors";
errs() << " ScalarizedVectors";
if (Mapped & 16)
cerr << " ExpandedIntegers";
errs() << " ExpandedIntegers";
if (Mapped & 32)
cerr << " ExpandedFloats";
errs() << " ExpandedFloats";
if (Mapped & 64)
cerr << " SplitVectors";
errs() << " SplitVectors";
if (Mapped & 128)
cerr << " WidenedVectors";
cerr << "\n";
errs() << " WidenedVectors";
errs() << "\n";
llvm_unreachable(0);
}
}
@ -337,7 +338,7 @@ ScanOperands:
}
if (i == NumOperands) {
DEBUG(cerr << "Legally typed node: "; N->dump(&DAG); cerr << "\n");
DEBUG(errs() << "Legally typed node: "; N->dump(&DAG); errs() << "\n");
}
}
NodeDone:
@ -406,7 +407,7 @@ NodeDone:
if (!IgnoreNodeResults(I))
for (unsigned i = 0, NumVals = I->getNumValues(); i < NumVals; ++i)
if (!isTypeLegal(I->getValueType(i))) {
cerr << "Result type " << i << " illegal!\n";
errs() << "Result type " << i << " illegal!\n";
Failed = true;
}
@ -414,24 +415,24 @@ NodeDone:
for (unsigned i = 0, NumOps = I->getNumOperands(); i < NumOps; ++i)
if (!IgnoreNodeResults(I->getOperand(i).getNode()) &&
!isTypeLegal(I->getOperand(i).getValueType())) {
cerr << "Operand type " << i << " illegal!\n";
errs() << "Operand type " << i << " illegal!\n";
Failed = true;
}
if (I->getNodeId() != Processed) {
if (I->getNodeId() == NewNode)
cerr << "New node not analyzed?\n";
errs() << "New node not analyzed?\n";
else if (I->getNodeId() == Unanalyzed)
cerr << "Unanalyzed node not noticed?\n";
errs() << "Unanalyzed node not noticed?\n";
else if (I->getNodeId() > 0)
cerr << "Operand not processed?\n";
errs() << "Operand not processed?\n";
else if (I->getNodeId() == ReadyToProcess)
cerr << "Not added to worklist?\n";
errs() << "Not added to worklist?\n";
Failed = true;
}
if (Failed) {
I->dump(&DAG); cerr << "\n";
I->dump(&DAG); errs() << "\n";
llvm_unreachable(0);
}
}

59
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -24,6 +24,7 @@
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
//===----------------------------------------------------------------------===//
@ -31,15 +32,17 @@ using namespace llvm;
//===----------------------------------------------------------------------===//
void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
cerr << "\n");
DEBUG(errs() << "Scalarize node result " << ResNo << ": ";
N->dump(&DAG);
errs() << "\n");
SDValue R = SDValue();
switch (N->getOpcode()) {
default:
#ifndef NDEBUG
cerr << "ScalarizeVectorResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
errs() << "ScalarizeVectorResult #" << ResNo << ": ";
N->dump(&DAG);
errs() << "\n";
#endif
llvm_unreachable("Do not know how to scalarize the result of this operator!");
@ -267,16 +270,18 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
//===----------------------------------------------------------------------===//
bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
cerr << "\n");
DEBUG(errs() << "Scalarize node operand " << OpNo << ": ";
N->dump(&DAG);
errs() << "\n");
SDValue Res = SDValue();
if (Res.getNode() == 0) {
switch (N->getOpcode()) {
default:
#ifndef NDEBUG
cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
errs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
N->dump(&DAG);
errs() << "\n";
#endif
llvm_unreachable("Do not know how to scalarize this operator's operand!");
case ISD::BIT_CONVERT:
@ -369,14 +374,17 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
/// legalization, we just know that (at least) one result needs vector
/// splitting.
void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
DEBUG(errs() << "Split node result: ";
N->dump(&DAG);
errs() << "\n");
SDValue Lo, Hi;
switch (N->getOpcode()) {
default:
#ifndef NDEBUG
cerr << "SplitVectorResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
errs() << "SplitVectorResult #" << ResNo << ": ";
N->dump(&DAG);
errs() << "\n";
#endif
llvm_unreachable("Do not know how to split the result of this operator!");
@ -917,15 +925,18 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
/// result types of the node are known to be legal, but other operands of the
/// node may need legalization as well as the specified one.
bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
DEBUG(errs() << "Split node operand: ";
N->dump(&DAG);
errs() << "\n");
SDValue Res = SDValue();
if (Res.getNode() == 0) {
switch (N->getOpcode()) {
default:
#ifndef NDEBUG
cerr << "SplitVectorOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
errs() << "SplitVectorOperand Op #" << OpNo << ": ";
N->dump(&DAG);
errs() << "\n";
#endif
llvm_unreachable("Do not know how to split this operator's operand!");
@ -1106,15 +1117,17 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
//===----------------------------------------------------------------------===//
void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Widen node result " << ResNo << ": "; N->dump(&DAG);
cerr << "\n");
DEBUG(errs() << "Widen node result " << ResNo << ": ";
N->dump(&DAG);
errs() << "\n");
SDValue Res = SDValue();
switch (N->getOpcode()) {
default:
#ifndef NDEBUG
cerr << "WidenVectorResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
errs() << "WidenVectorResult #" << ResNo << ": ";
N->dump(&DAG);
errs() << "\n";
#endif
llvm_unreachable("Do not know how to widen the result of this operator!");
@ -1762,15 +1775,17 @@ SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
// Widen Vector Operand
//===----------------------------------------------------------------------===//
bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
DEBUG(cerr << "Widen node operand " << ResNo << ": "; N->dump(&DAG);
cerr << "\n");
DEBUG(errs() << "Widen node operand " << ResNo << ": ";
N->dump(&DAG);
errs() << "\n");
SDValue Res = SDValue();
switch (N->getOpcode()) {
default:
#ifndef NDEBUG
cerr << "WidenVectorOperand op #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
errs() << "WidenVectorOperand op #" << ResNo << ": ";
N->dump(&DAG);
errs() << "\n";
#endif
llvm_unreachable("Do not know how to widen this operator's operand!");

12
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
View File

@ -138,9 +138,9 @@ void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) {
#ifndef NDEBUG
if (PredSU->NumSuccsLeft < 0) {
cerr << "*** Scheduling failed! ***\n";
errs() << "*** Scheduling failed! ***\n";
PredSU->dump(this);
cerr << " has been released too many times!\n";
errs() << " has been released too many times!\n";
llvm_unreachable(0);
}
#endif
@ -604,16 +604,16 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
continue;
}
if (!AnyNotSched)
cerr << "*** List scheduling failed! ***\n";
errs() << "*** List scheduling failed! ***\n";
SUnits[i].dump(this);
cerr << "has not been scheduled!\n";
errs() << "has not been scheduled!\n";
AnyNotSched = true;
}
if (SUnits[i].NumSuccsLeft != 0) {
if (!AnyNotSched)
cerr << "*** List scheduling failed! ***\n";
errs() << "*** List scheduling failed! ***\n";
SUnits[i].dump(this);
cerr << "has successors left!\n";
errs() << "has successors left!\n";
AnyNotSched = true;
}
}

4
lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
View File

@ -112,9 +112,9 @@ void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) {
#ifndef NDEBUG
if (SuccSU->NumPredsLeft < 0) {
cerr << "*** Scheduling failed! ***\n";
errs() << "*** Scheduling failed! ***\n";
SuccSU->dump(this);
cerr << " has been released too many times!\n";
errs() << " has been released too many times!\n";
llvm_unreachable(0);
}
#endif

8
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -201,9 +201,9 @@ void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
#ifndef NDEBUG
if (PredSU->NumSuccsLeft < 0) {
cerr << "*** Scheduling failed! ***\n";
errs() << "*** Scheduling failed! ***\n";
PredSU->dump(this);
cerr << " has been released too many times!\n";
errs() << " has been released too many times!\n";
llvm_unreachable(0);
}
#endif
@ -828,9 +828,9 @@ void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, const SDep *SuccEdge) {
#ifndef NDEBUG
if (SuccSU->NumPredsLeft < 0) {
cerr << "*** Scheduling failed! ***\n";
errs() << "*** Scheduling failed! ***\n";
SuccSU->dump(this);
cerr << " has been released too many times!\n";
errs() << " has been released too many times!\n";
llvm_unreachable(0);
}
#endif

10
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -155,7 +155,7 @@ namespace llvm {
MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) const {
#ifndef NDEBUG
cerr << "If a target marks an instruction with "
errs() << "If a target marks an instruction with "
"'usesCustomDAGSchedInserter', it must implement "
"TargetLowering::EmitInstrWithCustomInserter!";
#endif
@ -662,7 +662,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
I != E; ++I, ++j)
if (Fn.paramHasAttr(j, Attribute::ByVal)) {
if (EnableFastISelVerbose || EnableFastISelAbort)
cerr << "FastISel skips entry block due to byval argument\n";
errs() << "FastISel skips entry block due to byval argument\n";
SuppressFastISel = true;
break;
}
@ -727,7 +727,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
if (isa<TerminatorInst>(BI))
if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
if (EnableFastISelVerbose || EnableFastISelAbort) {
cerr << "FastISel miss: ";
errs() << "FastISel miss: ";
BI->dump();
}
assert(!EnableFastISelAbort &&
@ -746,7 +746,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
// Then handle certain instructions as single-LLVM-Instruction blocks.
if (isa<CallInst>(BI)) {
if (EnableFastISelVerbose || EnableFastISelAbort) {
cerr << "FastISel missed call: ";
errs() << "FastISel missed call: ";
BI->dump();
}
@ -768,7 +768,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
// For now, be a little lenient about non-branch terminators.
if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
if (EnableFastISelVerbose || EnableFastISelAbort) {
cerr << "FastISel miss: ";
errs() << "FastISel miss: ";
BI->dump();
}
if (EnableFastISelAbort)

6
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -520,7 +520,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
// Stack frame index must be less than 512 (divided by 16):
FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
int FI = int(FIN->getIndex());
DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
DEBUG(errs() << "SelectDFormAddr: ISD::FrameIndex = "
<< FI << "\n");
if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
Base = CurDAG->getTargetConstant(0, PtrTy);
@ -545,7 +545,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
if (Op0.getOpcode() == ISD::FrameIndex) {
FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
int FI = int(FIN->getIndex());
DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
<< " frame index = " << FI << "\n");
if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
@ -566,7 +566,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
if (Op1.getOpcode() == ISD::FrameIndex) {
FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
int FI = int(FIN->getIndex());
DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
<< " frame index = " << FI << "\n");
if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {

44
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -849,9 +849,9 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
// to the stack pointer, which is always aligned.
#if !defined(NDEBUG)
if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
cerr << "CellSPU LowerSTORE: basePtr = ";
errs() << "CellSPU LowerSTORE: basePtr = ";
basePtr.getNode()->dump(&DAG);
cerr << "\n";
errs() << "\n";
}
#endif
@ -874,9 +874,9 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
const SDValue &currentRoot = DAG.getRoot();
DAG.setRoot(result);
cerr << "------- CellSPU:LowerStore result:\n";
errs() << "------- CellSPU:LowerStore result:\n";
DAG.dump();
cerr << "-------\n";
errs() << "-------\n";
DAG.setRoot(currentRoot);
}
#endif
@ -2622,9 +2622,9 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
switch (Opc) {
default: {
#ifndef NDEBUG
cerr << "SPUTargetLowering::LowerOperation(): need to lower this!\n";
cerr << "Op.getOpcode() = " << Opc << "\n";
cerr << "*Op.getNode():\n";
errs() << "SPUTargetLowering::LowerOperation(): need to lower this!\n";
errs() << "Op.getOpcode() = " << Opc << "\n";
errs() << "*Op.getNode():\n";
Op.getNode()->dump();
#endif
llvm_unreachable(0);
@ -2715,9 +2715,9 @@ void SPUTargetLowering::ReplaceNodeResults(SDNode *N,
switch (Opc) {
default: {
cerr << "SPUTargetLowering::ReplaceNodeResults(): need to fix this!\n";
cerr << "Op.getOpcode() = " << Opc << "\n";
cerr << "*Op.getNode():\n";
errs() << "SPUTargetLowering::ReplaceNodeResults(): need to fix this!\n";
errs() << "Op.getOpcode() = " << Opc << "\n";
errs() << "*Op.getNode():\n";
N->dump();
abort();
/*NOTREACHED*/
@ -2771,7 +2771,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
#if !defined(NDEBUG)
if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
cerr << "\n"
errs() << "\n"
<< "Replace: (add (SPUindirect <arg>, <arg>), 0)\n"
<< "With: (SPUindirect <arg>, <arg>)\n";
}
@ -2787,7 +2787,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
#if !defined(NDEBUG)
if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
cerr << "\n"
errs() << "\n"
<< "Replace: (add (SPUindirect <arg>, " << CN1->getSExtValue()
<< "), " << CN0->getSExtValue() << ")\n"
<< "With: (SPUindirect <arg>, "
@ -2811,11 +2811,11 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
// Types must match, however...
#if !defined(NDEBUG)
if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
cerr << "\nReplace: ";
errs() << "\nReplace: ";
N->dump(&DAG);
cerr << "\nWith: ";
errs() << "\nWith: ";
Op0.getNode()->dump(&DAG);
cerr << "\n";
errs() << "\n";
}
#endif
@ -2830,11 +2830,11 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
// (SPUindirect (SPUaform <addr>, 0), 0) ->
// (SPUaform <addr>, 0)
DEBUG(cerr << "Replace: ");
DEBUG(errs() << "Replace: ");
DEBUG(N->dump(&DAG));
DEBUG(cerr << "\nWith: ");
DEBUG(errs() << "\nWith: ");
DEBUG(Op0.getNode()->dump(&DAG));
DEBUG(cerr << "\n");
DEBUG(errs() << "\n");
return Op0;
}
@ -2847,7 +2847,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
#if !defined(NDEBUG)
if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
cerr << "\n"
errs() << "\n"
<< "Replace: (SPUindirect (add <arg>, <arg>), 0)\n"
<< "With: (SPUindirect <arg>, <arg>)\n";
}
@ -2909,11 +2909,11 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
// Otherwise, return unchanged.
#ifndef NDEBUG
if (Result.getNode()) {
DEBUG(cerr << "\nReplace.SPU: ");
DEBUG(errs() << "\nReplace.SPU: ");
DEBUG(N->dump(&DAG));
DEBUG(cerr << "\nWith: ");
DEBUG(errs() << "\nWith: ");
DEBUG(Result.getNode()->dump(&DAG));
DEBUG(cerr << "\n");
DEBUG(errs() << "\n");
}
#endif

2
lib/Target/CellSPU/SPURegisterInfo.cpp
View File

@ -365,7 +365,7 @@ SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
SPOp.ChangeToRegister(SPU::R1, false);
if (Offset > SPUFrameInfo::maxFrameOffset()
|| Offset < SPUFrameInfo::minFrameOffset()) {
cerr << "Large stack adjustment ("
errs() << "Large stack adjustment ("
<< Offset
<< ") in SPURegisterInfo::eliminateFrameIndex.";
} else {

5
lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -34,6 +34,7 @@
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/VectorExtras.h"
using namespace llvm;
@ -225,7 +226,7 @@ MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
default:
{
#ifndef NDEBUG
cerr << "LowerFormalArguments Unhandled argument type: "
errs() << "LowerFormalArguments Unhandled argument type: "
<< RegVT.getSimpleVT().SimpleTy << "\n";
#endif
llvm_unreachable(0);
@ -257,7 +258,7 @@ MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
// Load the argument to a virtual register
unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
if (ObjSize > 2) {
cerr << "LowerFormalArguments Unhandled argument type: "
errs() << "LowerFormalArguments Unhandled argument type: "
<< VA.getLocVT().getSimpleVT().SimpleTy
<< "\n";
}

20
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -59,21 +59,23 @@ namespace {
}
void dump() {
cerr << "SystemZRRIAddressMode " << this << '\n';
errs() << "SystemZRRIAddressMode " << this << '\n';
if (BaseType == RegBase) {
cerr << "Base.Reg ";
if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump();
else cerr << "nul";
cerr << '\n';
errs() << "Base.Reg ";
if (Base.Reg.getNode() != 0)
Base.Reg.getNode()->dump();
else
errs() << "nul";
errs() << '\n';
} else {
cerr << " Base.FrameIndex " << Base.FrameIndex << '\n';
errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
}
if (!isRI) {
cerr << "IndexReg ";
errs() << "IndexReg ";
if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
else cerr << "nul";
else errs() << "nul";
}
cerr << " Disp " << Disp << '\n';
errs() << " Disp " << Disp << '\n';
}
};
}

3
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -34,6 +34,7 @@
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/VectorExtras.h"
using namespace llvm;
@ -289,7 +290,7 @@ SystemZTargetLowering::LowerCCCArguments(SDValue Chain,
switch (LocVT.getSimpleVT().SimpleTy) {
default:
#ifndef NDEBUG
cerr << "LowerFormalArguments Unhandled argument type: "
errs() << "LowerFormalArguments Unhandled argument type: "
<< LocVT.getSimpleVT().SimpleTy
<< "\n";
#endif

6
lib/Target/X86/X86FloatingPoint.cpp
View File

@ -76,12 +76,12 @@ namespace {
unsigned StackTop; // The current top of the FP stack.
void dumpStack() const {
cerr << "Stack contents:";
errs() << "Stack contents:";
for (unsigned i = 0; i != StackTop; ++i) {
cerr << " FP" << Stack[i];
errs() << " FP" << Stack[i];
assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
}
cerr << "\n";
errs() << "\n";
}
private:
/// isStackEmpty - Return true if the FP stack is empty.

4
lib/Target/XCore/XCoreRegisterInfo.cpp
View File

@ -145,8 +145,8 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
if (!isU6 && !isImmU16(Amount)) {
// FIX could emit multiple instructions in this case.
#ifndef NDEBUG
cerr << "eliminateCallFramePseudoInstr size too big: "
<< Amount << "\n";
errs() << "eliminateCallFramePseudoInstr size too big: "
<< Amount << "\n";
#endif
llvm_unreachable(0);
}

2
lib/Transforms/IPO/Internalize.cpp
View File

@ -87,7 +87,7 @@ void InternalizePass::LoadFile(const char *Filename) {
// Load the APIFile...
std::ifstream In(Filename);
if (!In.good()) {
cerr << "WARNING: Internalize couldn't load file '" << Filename
errs() << "WARNING: Internalize couldn't load file '" << Filename
<< "'! Continuing as if it's empty.\n";
return; // Just continue as if the file were empty
}

22
lib/Transforms/Scalar/PredicateSimplifier.cpp
View File

@ -277,16 +277,16 @@ namespace {
#ifndef NDEBUG
virtual void dump() const {
dump(*cerr.stream());
dump(errs());
}
void dump(std::ostream &os) const {
void dump(raw_ostream &os) const {
os << "Predicate simplifier DomTreeDFS: \n";
dump(Entry, 0, os);
os << "\n\n";
}
void dump(Node *N, int depth, std::ostream &os) const {
void dump(Node *N, int depth, raw_ostream &os) const {
++depth;
for (int i = 0; i < depth; ++i) { os << " "; }
os << "[" << depth << "] ";
@ -656,10 +656,10 @@ namespace {
#ifndef NDEBUG
virtual ~Node() {}
virtual void dump() const {
dump(*cerr.stream());
dump(errs());
}
private:
void dump(std::ostream &os) const {
void dump(raw_ostream &os) const {
static const std::string names[32] =
{ "000000", "000001", "000002", "000003", "000004", "000005",
"000006", "000007", "000008", "000009", " >", " >=",
@ -887,10 +887,10 @@ namespace {
#ifndef NDEBUG
virtual ~InequalityGraph() {}
virtual void dump() {
dump(*cerr.stream());
dump(errs());
}
void dump(std::ostream &os) {
void dump(raw_ostream &os) {
for (unsigned i = 1; i <= Nodes.size(); ++i) {
os << i << " = {";
node(i)->dump(os);
@ -923,10 +923,10 @@ namespace {
#ifndef NDEBUG
virtual ~ScopedRange() {}
virtual void dump() const {
dump(*cerr.stream());
dump(errs());
}
void dump(std::ostream &os) const {
void dump(raw_ostream &os) const {
os << "{";
for (const_iterator I = begin(), E = end(); I != E; ++I) {
os << &I->second << " (" << I->first->getDFSNumIn() << "), ";
@ -1035,10 +1035,10 @@ namespace {
virtual ~ValueRanges() {}
virtual void dump() const {
dump(*cerr.stream());
dump(errs());
}
void dump(std::ostream &os) const {
void dump(raw_ostream &os) const {
for (unsigned i = 0, e = Ranges.size(); i != e; ++i) {
os << (i+1) << " = ";
Ranges[i].dump(os);